From patchwork Thu Nov 19 15:55:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 11918909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73860C63777 for ; Thu, 19 Nov 2020 20:32:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F6452222F for ; Thu, 19 Nov 2020 20:32:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0F6452222F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=crapouillou.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D9136E81D; Thu, 19 Nov 2020 20:32:08 +0000 (UTC) Received: from aposti.net (aposti.net [89.234.176.197]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49AA86E536 for ; Thu, 19 Nov 2020 15:56:32 +0000 (UTC) From: Paul Cercueil To: David Airlie , Daniel Vetter Subject: [PATCH 3/3] drm/ingenic: Add support for serial 8-bit delta-RGB panels Date: Thu, 19 Nov 2020 15:55:59 +0000 Message-Id: <20201119155559.14112-4-paul@crapouillou.net> In-Reply-To: <20201119155559.14112-1-paul@crapouillou.net> References: <20201119155559.14112-1-paul@crapouillou.net> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 19 Nov 2020 20:32:07 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Cercueil , od@zcrc.me, Sam Ravnborg , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for 24-bit panels that are connected through a 8-bit bus and use delta-RGB, which means a RGB pixel ordering on odd lines, and a GBR pixel ordering on even lines. Signed-off-by: Paul Cercueil --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 7 ++++++- drivers/gpu/drm/ingenic/ingenic-drm.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 0b2311b32b81..fdce8a8f276a 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -589,7 +589,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode = &crtc_state->adjusted_mode; struct drm_connector *conn = conn_state->connector; struct drm_display_info *info = &conn->display_info; - unsigned int cfg; + unsigned int cfg, rgbcfg = 0; priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS; @@ -626,6 +626,9 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, case MEDIA_BUS_FMT_RGB888_1X24: cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT; break; + case MEDIA_BUS_FMT_RGB888_3X8_DELTA: + rgbcfg = JZ_LCD_RGBC_EVEN_GBR | JZ_LCD_RGBC_ODD_RGB; + fallthrough; case MEDIA_BUS_FMT_RGB888_3X8: cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL; break; @@ -636,6 +639,7 @@ static void ingenic_drm_encoder_atomic_mode_set(struct drm_encoder *encoder, } regmap_write(priv->map, JZ_REG_LCD_CFG, cfg); + regmap_write(priv->map, JZ_REG_LCD_RGBC, rgbcfg); } static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, @@ -653,6 +657,7 @@ static int ingenic_drm_encoder_atomic_check(struct drm_encoder *encoder, switch (*info->bus_formats) { case MEDIA_BUS_FMT_RGB888_3X8: + case MEDIA_BUS_FMT_RGB888_3X8_DELTA: /* * The LCD controller expects timing values in dot-clock ticks, * which is 3x the timing values in pixels when using a 3x8-bit diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h b/drivers/gpu/drm/ingenic/ingenic-drm.h index 9b48ce02803d..1b4347f7f084 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm.h +++ b/drivers/gpu/drm/ingenic/ingenic-drm.h @@ -31,6 +31,7 @@ #define JZ_REG_LCD_SA1 0x54 #define JZ_REG_LCD_FID1 0x58 #define JZ_REG_LCD_CMD1 0x5C +#define JZ_REG_LCD_RGBC 0x90 #define JZ_REG_LCD_OSDC 0x100 #define JZ_REG_LCD_OSDCTRL 0x104 #define JZ_REG_LCD_OSDS 0x108 @@ -138,6 +139,19 @@ #define JZ_LCD_STATE_SOF_IRQ BIT(4) #define JZ_LCD_STATE_DISABLED BIT(0) +#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4) +#define JZ_LCD_RGBC_ODD_RBG (0x1 << 4) +#define JZ_LCD_RGBC_ODD_GRB (0x2 << 4) +#define JZ_LCD_RGBC_ODD_GBR (0x3 << 4) +#define JZ_LCD_RGBC_ODD_BRG (0x4 << 4) +#define JZ_LCD_RGBC_ODD_BGR (0x5 << 4) +#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0) +#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0) +#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0) +#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0) +#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0) +#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) + #define JZ_LCD_OSDC_OSDEN BIT(0) #define JZ_LCD_OSDC_F0EN BIT(3) #define JZ_LCD_OSDC_F1EN BIT(4)