diff mbox series

[RFC,105/162] drm/i915: Provide a way to disable PCIe relaxed write ordering

Message ID 20201127120718.454037-106-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show
Series DG1 + LMEM enabling | expand

Commit Message

Matthew Auld Nov. 27, 2020, 12:06 p.m. UTC 
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

For performance writes over PCIe may not be strictly ordered by default.
This provides an option to expose a kernel configuration option to disable
relaxed ordering and turn on strict ordering instead for debug purposes.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.debug         | 11 +++++++++++
 drivers/gpu/drm/i915/intel_memory_region.c | 12 ++++++++++++
 2 files changed, 23 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 0fb7fd0ef717..65533cbbcb82 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -222,3 +222,14 @@  config DRM_I915_DEBUG_RUNTIME_PM
 	  driver loading, suspend and resume operations.
 
 	  If in doubt, say "N"
+
+config DRM_I915_PCIE_STRICT_WRITE_ORDERING
+	bool "Enable PCIe strict ordering "
+	depends on DRM_I915
+	default n
+	help
+	  Relaxed ordering in writes is enabled by default to improve system
+	  performance. Strict ordering can be selected instead to assist in
+	  debugging.
+
+	  If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index cea44ddebe46..043541d409bd 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -286,6 +286,18 @@  int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
 {
 	int err, i;
 
+	/* All platforms currently have system memory */
+	GEM_BUG_ON(!HAS_REGION(i915, REGION_SMEM));
+
+	if (IS_DGFX(i915)) {
+		if (IS_ENABLED(CONFIG_DRM_I915_PCIE_STRICT_WRITE_ORDERING))
+			pcie_capability_clear_word(i915->drm.pdev, PCI_EXP_DEVCTL,
+						   PCI_EXP_DEVCTL_RELAX_EN);
+		else
+			pcie_capability_set_word(i915->drm.pdev, PCI_EXP_DEVCTL,
+						 PCI_EXP_DEVCTL_RELAX_EN);
+	}
+
 	for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
 		struct intel_memory_region *mem = ERR_PTR(-ENODEV);
 		u16 type, instance;