| Message ID | 20210208185557.15703-1-jonathan@marek.ca (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm: fix a6xx_gmu_clear_oob | expand |
On Mon, Feb 08, 2021 at 01:55:54PM -0500, Jonathan Marek wrote: > The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing > bitshift operation. > > Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling") > Signed-off-by: Jonathan Marek <jonathan@marek.ca> Thanks. I feel silly that I missed that. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 71c917f909af..91cf46f84025 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) > else > bit = a6xx_gmu_oob_bits[state].ack_new; > > - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); > + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); > } > > /* Enable CPU control of SPTP power power collapse */ > -- > 2.26.1 >
On Tue, Feb 9, 2021 at 5:24 PM Jordan Crouse <jcrouse@codeaurora.org> wrote: > > On Mon, Feb 08, 2021 at 01:55:54PM -0500, Jonathan Marek wrote: > > The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing > > bitshift operation. > > > > Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling") > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > > Thanks. I feel silly that I missed that. > > Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Yeah, oops. Reviewed-by: Eric Anholt <eric@anholt.net>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 71c917f909af..91cf46f84025 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) else bit = a6xx_gmu_oob_bits[state].ack_new; - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); } /* Enable CPU control of SPTP power power collapse */
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing bitshift operation. Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling") Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)