| Message ID | 20210213101512.3275069-2-mperttunen@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | NVIDIA Tegra NVDEC support | expand |
On 13/02/2021 11:15, Mikko Perttunen wrote: > Convert the original Host1x bindings to YAML and add new bindings for > NVDEC, now in a more appropriate location. The old text bindings > for Host1x and engines are still kept at display/tegra/ since they > encompass a lot more engines that haven't been converted over yet. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ > .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 220 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > new file mode 100644 > index 000000000000..613c6601f0f1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > @@ -0,0 +1,129 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra20-host1x.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Device tree binding for NVIDIA Host1x > + > +maintainers: > + - Thierry Reding <treding@gmail.com> > + - Mikko Perttunen <mperttunen@nvidia.com> > + > +properties: > + $nodename: > + pattern: "^host1x@[0-9a-f]*$" > + > + compatible: > + oneOf: > + - const: nvidia,tegra20-host1x > + - const: nvidia,tegra30-host1x > + - const: nvidia,tegra114-host1x > + - const: nvidia,tegra124-host1x > + - items: > + - const: nvidia,tegra132-host1x > + - const: nvidia,tegra124-host1x > + - const: nvidia,tegra210-host1x > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: Syncpoint threshold interrupt > + - description: General interrupt > + > + interrupt-names: > + items: > + - const: syncpt > + - const: host1x > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: host1x > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: host1x > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 1 > + > + interconnect-names: > + items: > + - const: dma-mem > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 1 > + > + ranges: true > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - resets > + - reset-names > + - '#address-cells' > + - '#size-cells' > + - ranges > + > +additionalProperties: > + type: object > + > +if: > + properties: > + compatible: > + contains: > + anyOf: > + - const: nvidia,tegra186-host1x > + - const: nvidia,tegra194-host1x > +then: > + properties: > + reg: > + items: > + - description: Hypervisor-accessible register area > + - description: VM-accessible register area > + reg-names: > + items: > + - const: hypervisor > + - const: vm > + required: > + - reg-names > + > +examples: > + - | > + #include <dt-bindings/clock/tegra20-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + host1x@50000000 { > + compatible = "nvidia,tegra20-host1x"; > + reg = <0x50000000 0x00024000>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ > + interrupt-names = "syncpt", "host1x"; > + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; > + clock-names = "host1x"; > + resets = <&tegra_car 28>; > + reset-names = "host1x"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0x54000000 0x54000000 0x04000000>; > + }; > diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > new file mode 100644 > index 000000000000..9a6334d930c8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Device tree binding for NVIDIA Tegra VIC -----------------------------------------------/\ Should be NVDEC ? Neil > + > +maintainers: > + - Thierry Reding <treding@gmail.com> > + - Mikko Perttunen <mperttunen@nvidia.com> > + > +properties: > + $nodename: > + pattern: "^nvdec@[0-9a-f]*$" > + > + compatible: > + enum: > + - nvidia,tegra210-nvdec > + - nvidia,tegra186-nvdec > + - nvidia,tegra194-nvdec > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: nvdec > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: nvdec > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + interconnects: > + items: > + - description: DMA read memory client > + - description: DMA write memory client > + > + interconnect-names: > + items: > + - const: dma-mem > + - const: write > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/tegra186-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/tegra186-mc.h> > + #include <dt-bindings/power/tegra186-powergate.h> > + #include <dt-bindings/reset/tegra186-reset.h> > + > + nvdec@15480000 { > + compatible = "nvidia,tegra186-nvdec"; > + reg = <0x15480000 0x40000>; > + clocks = <&bpmp TEGRA186_CLK_NVDEC>; > + clock-names = "nvdec"; > + resets = <&bpmp TEGRA186_RESET_NVDEC>; > + reset-names = "nvdec"; > + > + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; > + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, > + <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; > + interconnect-names = "dma-mem", "write"; > + iommus = <&smmu TEGRA186_SID_NVDEC>; > + }; > + > + > diff --git a/MAINTAINERS b/MAINTAINERS > index 8170b40d6236..b892419c6564 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5950,6 +5950,7 @@ L: linux-tegra@vger.kernel.org > S: Supported > T: git git://anongit.freedesktop.org/tegra/linux.git > F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +F: Documentation/devicetree/bindings/gpu/host1x/ > F: drivers/gpu/drm/tegra/ > F: drivers/gpu/host1x/ > F: include/linux/host1x.h >
On Sat, 13 Feb 2021 12:15:10 +0200, Mikko Perttunen wrote: > Convert the original Host1x bindings to YAML and add new bindings for > NVDEC, now in a more appropriate location. The old text bindings > for Host1x and engines are still kept at display/tegra/ since they > encompass a lot more engines that haven't been converted over yet. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ > .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 220 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml:90:1: [warning] too many blank lines (2 > 1) (empty-lines) dtschema/dtc warnings/errors: See https://patchwork.ozlabs.org/patch/1440164 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Sat, Feb 13, 2021 at 12:15:10PM +0200, Mikko Perttunen wrote: > Convert the original Host1x bindings to YAML and add new bindings for > NVDEC, now in a more appropriate location. The old text bindings > for Host1x and engines are still kept at display/tegra/ since they > encompass a lot more engines that haven't been converted over yet. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ > .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ > MAINTAINERS | 1 + > 3 files changed, 220 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > new file mode 100644 > index 000000000000..613c6601f0f1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > @@ -0,0 +1,129 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra20-host1x.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Device tree binding for NVIDIA Host1x > + > +maintainers: > + - Thierry Reding <treding@gmail.com> > + - Mikko Perttunen <mperttunen@nvidia.com> > + > +properties: > + $nodename: > + pattern: "^host1x@[0-9a-f]*$" > + > + compatible: > + oneOf: > + - const: nvidia,tegra20-host1x > + - const: nvidia,tegra30-host1x > + - const: nvidia,tegra114-host1x > + - const: nvidia,tegra124-host1x > + - items: > + - const: nvidia,tegra132-host1x > + - const: nvidia,tegra124-host1x > + - const: nvidia,tegra210-host1x > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: Syncpoint threshold interrupt > + - description: General interrupt > + > + interrupt-names: > + items: > + - const: syncpt > + - const: host1x > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: host1x > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: host1x > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 1 > + > + interconnect-names: > + items: > + - const: dma-mem > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 1 > + > + ranges: true > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - resets > + - reset-names > + - '#address-cells' > + - '#size-cells' > + - ranges > + > +additionalProperties: > + type: object > + > +if: > + properties: > + compatible: > + contains: > + anyOf: > + - const: nvidia,tegra186-host1x > + - const: nvidia,tegra194-host1x Just use 'enum' instead of 'anyOf' and 'const'. > +then: > + properties: > + reg: > + items: > + - description: Hypervisor-accessible register area > + - description: VM-accessible register area If you test this, it will fail due to the 'maxItems: 1' above. The main section has to pass for all conditions and then if/them schema add constraints. > + reg-names: > + items: > + - const: hypervisor > + - const: vm > + required: > + - reg-names > + > +examples: > + - | > + #include <dt-bindings/clock/tegra20-car.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + host1x@50000000 { > + compatible = "nvidia,tegra20-host1x"; > + reg = <0x50000000 0x00024000>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ > + interrupt-names = "syncpt", "host1x"; > + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; > + clock-names = "host1x"; > + resets = <&tegra_car 28>; > + reset-names = "host1x"; > + > + #address-cells = <1>; > + #size-cells = <1>; > + > + ranges = <0x54000000 0x54000000 0x04000000>; > + }; > diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > new file mode 100644 > index 000000000000..9a6334d930c8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > @@ -0,0 +1,90 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Device tree binding for NVIDIA Tegra VIC I'm left wondering what NVDEC and VIC are? > + > +maintainers: > + - Thierry Reding <treding@gmail.com> > + - Mikko Perttunen <mperttunen@nvidia.com> > + > +properties: > + $nodename: > + pattern: "^nvdec@[0-9a-f]*$" > + > + compatible: > + enum: > + - nvidia,tegra210-nvdec > + - nvidia,tegra186-nvdec > + - nvidia,tegra194-nvdec > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: nvdec > + > + resets: > + maxItems: 1 > + > + reset-names: > + items: > + - const: nvdec > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + interconnects: > + items: > + - description: DMA read memory client > + - description: DMA write memory client > + > + interconnect-names: > + items: > + - const: dma-mem > + - const: write > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/tegra186-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/tegra186-mc.h> > + #include <dt-bindings/power/tegra186-powergate.h> > + #include <dt-bindings/reset/tegra186-reset.h> > + > + nvdec@15480000 { > + compatible = "nvidia,tegra186-nvdec"; > + reg = <0x15480000 0x40000>; > + clocks = <&bpmp TEGRA186_CLK_NVDEC>; > + clock-names = "nvdec"; > + resets = <&bpmp TEGRA186_RESET_NVDEC>; > + reset-names = "nvdec"; > + > + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; > + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, > + <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; > + interconnect-names = "dma-mem", "write"; > + iommus = <&smmu TEGRA186_SID_NVDEC>; > + }; > + > + > diff --git a/MAINTAINERS b/MAINTAINERS > index 8170b40d6236..b892419c6564 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -5950,6 +5950,7 @@ L: linux-tegra@vger.kernel.org > S: Supported > T: git git://anongit.freedesktop.org/tegra/linux.git > F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt > +F: Documentation/devicetree/bindings/gpu/host1x/ > F: drivers/gpu/drm/tegra/ > F: drivers/gpu/host1x/ > F: include/linux/host1x.h > -- > 2.30.0 >
On 2/17/21 11:49 PM, Rob Herring wrote: > On Sat, Feb 13, 2021 at 12:15:10PM +0200, Mikko Perttunen wrote: >> Convert the original Host1x bindings to YAML and add new bindings for >> NVDEC, now in a more appropriate location. The old text bindings >> for Host1x and engines are still kept at display/tegra/ since they >> encompass a lot more engines that haven't been converted over yet. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> --- >> .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ >> .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ >> MAINTAINERS | 1 + >> 3 files changed, 220 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml >> create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml >> >> diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml >> new file mode 100644 >> index 000000000000..613c6601f0f1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml >> @@ -0,0 +1,129 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra20-host1x.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Device tree binding for NVIDIA Host1x >> + >> +maintainers: >> + - Thierry Reding <treding@gmail.com> >> + - Mikko Perttunen <mperttunen@nvidia.com> >> + >> +properties: >> + $nodename: >> + pattern: "^host1x@[0-9a-f]*$" >> + >> + compatible: >> + oneOf: >> + - const: nvidia,tegra20-host1x >> + - const: nvidia,tegra30-host1x >> + - const: nvidia,tegra114-host1x >> + - const: nvidia,tegra124-host1x >> + - items: >> + - const: nvidia,tegra132-host1x >> + - const: nvidia,tegra124-host1x >> + - const: nvidia,tegra210-host1x >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + items: >> + - description: Syncpoint threshold interrupt >> + - description: General interrupt >> + >> + interrupt-names: >> + items: >> + - const: syncpt >> + - const: host1x >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: host1x >> + >> + resets: >> + maxItems: 1 >> + >> + reset-names: >> + items: >> + - const: host1x >> + >> + iommus: >> + maxItems: 1 >> + >> + interconnects: >> + maxItems: 1 >> + >> + interconnect-names: >> + items: >> + - const: dma-mem >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 1 >> + >> + ranges: true >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - interrupt-names >> + - clocks >> + - clock-names >> + - resets >> + - reset-names >> + - '#address-cells' >> + - '#size-cells' >> + - ranges >> + >> +additionalProperties: >> + type: object >> + >> +if: >> + properties: >> + compatible: >> + contains: >> + anyOf: >> + - const: nvidia,tegra186-host1x >> + - const: nvidia,tegra194-host1x > > Just use 'enum' instead of 'anyOf' and 'const'. Yep, will fix. > >> +then: >> + properties: >> + reg: >> + items: >> + - description: Hypervisor-accessible register area >> + - description: VM-accessible register area > > If you test this, it will fail due to the 'maxItems: 1' above. The main > section has to pass for all conditions and then if/them schema add > constraints. Interesting, I did run the schema check and DTB check but I didn't see issues there. In any case, will fix. > >> + reg-names: >> + items: >> + - const: hypervisor >> + - const: vm >> + required: >> + - reg-names >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/tegra20-car.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + host1x@50000000 { >> + compatible = "nvidia,tegra20-host1x"; >> + reg = <0x50000000 0x00024000>; >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ >> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ >> + interrupt-names = "syncpt", "host1x"; >> + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; >> + clock-names = "host1x"; >> + resets = <&tegra_car 28>; >> + reset-names = "host1x"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ranges = <0x54000000 0x54000000 0x04000000>; >> + }; >> diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml >> new file mode 100644 >> index 000000000000..9a6334d930c8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml >> @@ -0,0 +1,90 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >> + >> +title: Device tree binding for NVIDIA Tegra VIC > > I'm left wondering what NVDEC and VIC are? Accidentally left VIC here. Will fix and add some more description. FWIW, VIC is Video Image Compositor, and NVDEC is the HW video decoder on Tegra systems. Thanks for reviewing! Mikko > >> + >> +maintainers: >> + - Thierry Reding <treding@gmail.com> >> + - Mikko Perttunen <mperttunen@nvidia.com> >> + >> +properties: >> + $nodename: >> + pattern: "^nvdec@[0-9a-f]*$" >> + >> + compatible: >> + enum: >> + - nvidia,tegra210-nvdec >> + - nvidia,tegra186-nvdec >> + - nvidia,tegra194-nvdec >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: nvdec >> + >> + resets: >> + maxItems: 1 >> + >> + reset-names: >> + items: >> + - const: nvdec >> + >> + power-domains: >> + maxItems: 1 >> + >> + iommus: >> + maxItems: 1 >> + >> + interconnects: >> + items: >> + - description: DMA read memory client >> + - description: DMA write memory client >> + >> + interconnect-names: >> + items: >> + - const: dma-mem >> + - const: write >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - resets >> + - reset-names >> + - power-domains >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/tegra186-clock.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/memory/tegra186-mc.h> >> + #include <dt-bindings/power/tegra186-powergate.h> >> + #include <dt-bindings/reset/tegra186-reset.h> >> + >> + nvdec@15480000 { >> + compatible = "nvidia,tegra186-nvdec"; >> + reg = <0x15480000 0x40000>; >> + clocks = <&bpmp TEGRA186_CLK_NVDEC>; >> + clock-names = "nvdec"; >> + resets = <&bpmp TEGRA186_RESET_NVDEC>; >> + reset-names = "nvdec"; >> + >> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; >> + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, >> + <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; >> + interconnect-names = "dma-mem", "write"; >> + iommus = <&smmu TEGRA186_SID_NVDEC>; >> + }; >> + >> + >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 8170b40d6236..b892419c6564 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -5950,6 +5950,7 @@ L: linux-tegra@vger.kernel.org >> S: Supported >> T: git git://anongit.freedesktop.org/tegra/linux.git >> F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt >> +F: Documentation/devicetree/bindings/gpu/host1x/ >> F: drivers/gpu/drm/tegra/ >> F: drivers/gpu/host1x/ >> F: include/linux/host1x.h >> -- >> 2.30.0 >>
On Thu, Feb 18, 2021 at 5:04 AM Mikko Perttunen <cyndis@kapsi.fi> wrote: > > On 2/17/21 11:49 PM, Rob Herring wrote: > > On Sat, Feb 13, 2021 at 12:15:10PM +0200, Mikko Perttunen wrote: > >> Convert the original Host1x bindings to YAML and add new bindings for > >> NVDEC, now in a more appropriate location. The old text bindings > >> for Host1x and engines are still kept at display/tegra/ since they > >> encompass a lot more engines that haven't been converted over yet. > >> > >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > >> --- > >> .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ > >> .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ > >> MAINTAINERS | 1 + > >> 3 files changed, 220 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > >> create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > >> new file mode 100644 > >> index 000000000000..613c6601f0f1 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml > >> @@ -0,0 +1,129 @@ > >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra20-host1x.yaml#" > >> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > >> + > >> +title: Device tree binding for NVIDIA Host1x > >> + > >> +maintainers: > >> + - Thierry Reding <treding@gmail.com> > >> + - Mikko Perttunen <mperttunen@nvidia.com> > >> + > >> +properties: > >> + $nodename: > >> + pattern: "^host1x@[0-9a-f]*$" > >> + > >> + compatible: > >> + oneOf: > >> + - const: nvidia,tegra20-host1x > >> + - const: nvidia,tegra30-host1x > >> + - const: nvidia,tegra114-host1x > >> + - const: nvidia,tegra124-host1x > >> + - items: > >> + - const: nvidia,tegra132-host1x > >> + - const: nvidia,tegra124-host1x > >> + - const: nvidia,tegra210-host1x > >> + > >> + reg: > >> + maxItems: 1 > >> + > >> + interrupts: > >> + items: > >> + - description: Syncpoint threshold interrupt > >> + - description: General interrupt > >> + > >> + interrupt-names: > >> + items: > >> + - const: syncpt > >> + - const: host1x > >> + > >> + clocks: > >> + maxItems: 1 > >> + > >> + clock-names: > >> + items: > >> + - const: host1x > >> + > >> + resets: > >> + maxItems: 1 > >> + > >> + reset-names: > >> + items: > >> + - const: host1x > >> + > >> + iommus: > >> + maxItems: 1 > >> + > >> + interconnects: > >> + maxItems: 1 > >> + > >> + interconnect-names: > >> + items: > >> + - const: dma-mem > >> + > >> + '#address-cells': > >> + const: 1 > >> + > >> + '#size-cells': > >> + const: 1 > >> + > >> + ranges: true > >> + > >> +required: > >> + - compatible > >> + - reg > >> + - interrupts > >> + - interrupt-names > >> + - clocks > >> + - clock-names > >> + - resets > >> + - reset-names > >> + - '#address-cells' > >> + - '#size-cells' > >> + - ranges > >> + > >> +additionalProperties: > >> + type: object > >> + > >> +if: > >> + properties: > >> + compatible: > >> + contains: > >> + anyOf: > >> + - const: nvidia,tegra186-host1x > >> + - const: nvidia,tegra194-host1x > > > > Just use 'enum' instead of 'anyOf' and 'const'. > > Yep, will fix. > > > > >> +then: > >> + properties: > >> + reg: > >> + items: > >> + - description: Hypervisor-accessible register area > >> + - description: VM-accessible register area > > > > If you test this, it will fail due to the 'maxItems: 1' above. The main > > section has to pass for all conditions and then if/them schema add > > constraints. > > Interesting, I did run the schema check and DTB check but I didn't see > issues there. In any case, will fix. It may pass if you had 'reg = <base1 size1 base2 size2>' rather than 'reg = <base1 size1>, <base2 size2>'. While the bracketing doesn't matter for dtbs, it does currently for the schema. Rob
diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml new file mode 100644 index 000000000000..613c6601f0f1 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra20-host1x.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Host1x + +maintainers: + - Thierry Reding <treding@gmail.com> + - Mikko Perttunen <mperttunen@nvidia.com> + +properties: + $nodename: + pattern: "^host1x@[0-9a-f]*$" + + compatible: + oneOf: + - const: nvidia,tegra20-host1x + - const: nvidia,tegra30-host1x + - const: nvidia,tegra114-host1x + - const: nvidia,tegra124-host1x + - items: + - const: nvidia,tegra132-host1x + - const: nvidia,tegra124-host1x + - const: nvidia,tegra210-host1x + + reg: + maxItems: 1 + + interrupts: + items: + - description: Syncpoint threshold interrupt + - description: General interrupt + + interrupt-names: + items: + - const: syncpt + - const: host1x + + clocks: + maxItems: 1 + + clock-names: + items: + - const: host1x + + resets: + maxItems: 1 + + reset-names: + items: + - const: host1x + + iommus: + maxItems: 1 + + interconnects: + maxItems: 1 + + interconnect-names: + items: + - const: dma-mem + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: + type: object + +if: + properties: + compatible: + contains: + anyOf: + - const: nvidia,tegra186-host1x + - const: nvidia,tegra194-host1x +then: + properties: + reg: + items: + - description: Hypervisor-accessible register area + - description: VM-accessible register area + reg-names: + items: + - const: hypervisor + - const: vm + required: + - reg-names + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + host1x@50000000 { + compatible = "nvidia,tegra20-host1x"; + reg = <0x50000000 0x00024000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ + interrupt-names = "syncpt", "host1x"; + clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x04000000>; + }; diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml new file mode 100644 index 000000000000..9a6334d930c8 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra VIC + +maintainers: + - Thierry Reding <treding@gmail.com> + - Mikko Perttunen <mperttunen@nvidia.com> + +properties: + $nodename: + pattern: "^nvdec@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvdec + - nvidia,tegra186-nvdec + - nvidia,tegra194-nvdec + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvdec + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvdec + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra186-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/power/tegra186-powergate.h> + #include <dt-bindings/reset/tegra186-reset.h> + + nvdec@15480000 { + compatible = "nvidia,tegra186-nvdec"; + reg = <0x15480000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVDEC>; + clock-names = "nvdec"; + resets = <&bpmp TEGRA186_RESET_NVDEC>; + reset-names = "nvdec"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVDEC>; + }; + + diff --git a/MAINTAINERS b/MAINTAINERS index 8170b40d6236..b892419c6564 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5950,6 +5950,7 @@ L: linux-tegra@vger.kernel.org S: Supported T: git git://anongit.freedesktop.org/tegra/linux.git F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +F: Documentation/devicetree/bindings/gpu/host1x/ F: drivers/gpu/drm/tegra/ F: drivers/gpu/host1x/ F: include/linux/host1x.h
Convert the original Host1x bindings to YAML and add new bindings for NVDEC, now in a more appropriate location. The old text bindings for Host1x and engines are still kept at display/tegra/ since they encompass a lot more engines that haven't been converted over yet. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- .../gpu/host1x/nvidia,tegra20-host1x.yaml | 129 ++++++++++++++++++ .../gpu/host1x/nvidia,tegra210-nvdec.yaml | 90 ++++++++++++ MAINTAINERS | 1 + 3 files changed, 220 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra20-host1x.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml