From patchwork Mon Apr 12 09:05:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12197261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 736DAC43462 for ; Mon, 12 Apr 2021 09:10:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23E6661019 for ; Mon, 12 Apr 2021 09:10:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23E6661019 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 03C336E3C4; Mon, 12 Apr 2021 09:09:47 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 822B86E2ED; Mon, 12 Apr 2021 09:09:44 +0000 (UTC) IronPort-SDR: SPDvyJJS8cgvLD4QSehlc0VwhyquhYZWpp817FQB/fq/vIbBMPrfZ7YG8amIJOexaV65YR+t2B 5sligoYiv3kg== X-IronPort-AV: E=McAfee;i="6000,8403,9951"; a="193709753" X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="193709753" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 02:09:44 -0700 IronPort-SDR: yPcAYIIchguSNbPO4TosII0vIxrcsH1/JwaB9OeTyw3Im5377TfmAlq0oVMmwZeXDpjOhSMxPg nd/zKxkErPYg== X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="423712777" Received: from tarynrox-mobl1.ger.corp.intel.com (HELO mwauld-desk1.ger.corp.intel.com) ([10.252.5.30]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 02:09:42 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH 15/19] drm/i915: WA for zero memory channel Date: Mon, 12 Apr 2021 10:05:22 +0100 Message-Id: <20210412090526.30547-16-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210412090526.30547-1-matthew.auld@intel.com> References: <20210412090526.30547-1-matthew.auld@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , =?utf-8?q?Jos=C3=A9_Roberto_?= =?utf-8?q?de_Souza?= , Stanislav Lisovskiy , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: José Roberto de Souza Commit c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL") assumes that we always have a non-zero dram_info->channels and uses it as a divisor. We need num memory channels to be at least 1 for sane bw limits checking, even when PCode returns 0, so lets force it to 1 in this case. Cc: Stanislav Lisovskiy Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_bw.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 584ab5ce4106..c5f70f3e930e 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -175,6 +175,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel "Failed to get memory subsystem information, ignoring bandwidth limits"); return ret; } + num_channels = max_t(u8, 1, num_channels); deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); dclk_max = icl_sagv_max_dclk(&qi);