From patchwork Mon Apr 12 09:05:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12197265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9618AC43461 for ; Mon, 12 Apr 2021 09:10:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4FC026109E for ; Mon, 12 Apr 2021 09:10:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4FC026109E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A59D86E3D2; Mon, 12 Apr 2021 09:09:52 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31A466E3B7; Mon, 12 Apr 2021 09:09:50 +0000 (UTC) IronPort-SDR: r66JqcCBvvyNjtQUNBgQCJsIT7LSKZpQ545djwmdp77rYHjokK5xXQhYZTJ+HUuubrzY0ByVMQ TwjmUtMMMcmQ== X-IronPort-AV: E=McAfee;i="6000,8403,9951"; a="193709761" X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="193709761" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 02:09:48 -0700 IronPort-SDR: BIP4749M+J0Lg7YCjZKf0z120or4wScet2JZGq0AKagnVn5WULx7Uc1X3Cqwl3V3vYr0hhGIYO 1CUE5s5hOjIg== X-IronPort-AV: E=Sophos;i="5.82,216,1613462400"; d="scan'208";a="423712803" Received: from tarynrox-mobl1.ger.corp.intel.com (HELO mwauld-desk1.ger.corp.intel.com) ([10.252.5.30]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2021 02:09:46 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Subject: [PATCH 17/19] drm/i915/dg1: Double memory bandwidth available Date: Mon, 12 Apr 2021 10:05:24 +0100 Message-Id: <20210412090526.30547-18-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210412090526.30547-1-matthew.auld@intel.com> References: <20210412090526.30547-1-matthew.auld@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Swati Sharma , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Clint Taylor Use MCHBAR Gear_type information to compute memory bandwidth available during MCHBAR calculations. v2 by Jani: - switch to intel_uncore_read/intel_uncore_write Tested-by: Swati Sharma Cc: Swati Sharma Cc: Ville Syrjälä Signed-off-by: Clint Taylor Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 99cae0dc0ca2..6c02bd52ce45 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -41,6 +41,9 @@ struct intel_qgv_info { #define DG1_DRAM_T_RP_MASK (0x7F << 0) #define DG1_DRAM_T_RP_SHIFT 0 +#define ICL_GEAR_TYPE_MASK (0x01 << 16) +#define ICL_GEAR_TYPE_SHIFT 16 + static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, struct intel_qgv_point *sp, int point) @@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, else dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ sp->dclk = dclk_ratio * dclk_reference; + + val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT) + sp->dclk *= 2; + if (sp->dclk == 0) return -EINVAL;