| Message ID | 20210507092708.39552-1-kuohsiang_chou@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] drm/ast: Disable fast reset after DRAM initial | expand |
-----Original Message----- From: Kuo-Hsiang Chou Sent: Friday, May 07, 2021 5:27 PM To: tzimmermann@suse.de; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org Cc: airlied@redhat.com; airlied@linux.ie; daniel@ffwll.ch; Jenmin Yuan <jenmin_yuan@aspeedtech.com>; Kuo-Hsiang Chou <kuohsiang_chou@aspeedtech.com>; Arc Sung <arc_sung@aspeedtech.com> Subject: [PATCH v4] drm/ast: Disable fast reset after DRAM initial Hi Thomas, May I know if this patch has sth wrong. Or something I need to improve on it, I can fix it right now. Thanks! Regards, Kuo-Hsiang Chou [Bug][AST2500] V1: When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization have to be achieved by VGA driver with P2A (PCI to AHB) enabling. However, HW suggests disable Fast reset mode after DRAM initializaton, because fast reset mode is mainly designed for ARM ICE debugger. Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be first enabled to avoid system deadlock before disable fast reset mode. V2: Use to_pci_dev() to get revision of PCI configuration. V3: If SCU00 is not unlocked, just enter its password again. It is unnecessary to clear AHB lock condition and restore WDT default setting again, before Fast-reset clearing. V4: repatch after "error : could not build fake ancestor" resolved. Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> --- drivers/gpu/drm/ast/ast_drv.h | 1 + drivers/gpu/drm/ast/ast_main.c | 4 ++ drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++------------- 3 files changed, 47 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 911f9f414..5ebb5905d 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -346,6 +346,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); +void ast_patch_ahb_2500(struct ast_private *ast); /* ast dp501 */ void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 2aff2e6cf..cfb56ea3a 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -97,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Patch AST2500 */ + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) + ast_patch_ahb_2500(ast); + /* Double check it's actually working */ data = ast_read32(ast, 0xf004); if ((data != 0xFFFFFFFF) && (data != 0x00)) { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 0607658dd..56428798a 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -2028,6 +2028,30 @@ static bool ast_dram_init_2500(struct ast_private *ast) return true; } +void ast_patch_ahb_2500(struct ast_private *ast) { + u32 data; + + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2070); + if (data & 0x08000000) { /* check fast reset */ + + ast_moutdwm(ast, 0x1E785004, 0x00000010); + ast_moutdwm(ast, 0x1E785008, 0x00004755); + ast_moutdwm(ast, 0x1E78500c, 0x00000033); + udelay(1000); + } + do { + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2000); + } while (data != 1); + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ +} + void ast_post_chip_2500(struct drm_device *dev) { struct ast_private *ast = to_ast_private(dev); @@ -2035,39 +2059,31 @@ void ast_post_chip_2500(struct drm_device *dev) u8 reg; reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); - if ((reg & 0x80) == 0) {/* vga only */ + if ((reg & 0xC0) == 0) {/* vga only */ /* Clear bus lock condition */ - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); - ast_moutdwm(ast, 0x1e600084, 0x00010000); - ast_moutdwm(ast, 0x1e600088, 0x00000000); - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); - while (ast_read32(ast, 0x12000) != 0x1) - ; - - ast_write32(ast, 0x10000, 0xfc600309); - while (ast_read32(ast, 0x10000) != 0x1) - ; + ast_patch_ahb_2500(ast); + + /* Disable watchdog */ + ast_moutdwm(ast, 0x1E78502C, 0x00000000); + ast_moutdwm(ast, 0x1E78504C, 0x00000000); + /* Reset USB port */ + ast_moutdwm(ast, 0x1E6E2090, 0x20000000); + ast_moutdwm(ast, 0x1E6E2094, 0x00004000); + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { + ast_moutdwm(ast, 0x1E6E207C, 0x00800000); + mdelay(100); + ast_moutdwm(ast, 0x1E6E2070, 0x00800000); + } + /* Modify eSPI reset pin */ + temp = ast_mindwm(ast, 0x1E6E2070); + if (temp & 0x02000000) + ast_moutdwm(ast, 0x1E6E207C, 0x00004000); /* Slow down CPU/AHB CLK in VGA only mode */ temp = ast_read32(ast, 0x12008); temp |= 0x73; ast_write32(ast, 0x12008, temp); - /* Reset USB port to patch USB unknown device issue */ - ast_moutdwm(ast, 0x1e6e2090, 0x20000000); - temp = ast_mindwm(ast, 0x1e6e2094); - temp |= 0x00004000; - ast_moutdwm(ast, 0x1e6e2094, temp); - temp = ast_mindwm(ast, 0x1e6e2070); - if (temp & 0x00800000) { - ast_moutdwm(ast, 0x1e6e207c, 0x00800000); - mdelay(100); - ast_moutdwm(ast, 0x1e6e2070, 0x00800000); - } - if (!ast_dram_init_2500(ast)) drm_err(dev, "DRAM init failed !\n"); -- 2.18.4
Hi Thomas, May I know if I need to port this patch to the latest drm-misc-next again, because the patch has send to review for a while. If the porting or any other thing can reduce your review effort, please instruct me. Thanks! Best Regards, Kuo-Hsiang Chou -----Original Message----- From: dri-devel [mailto:dri-devel-bounces@lists.freedesktop.org] On Behalf Of Kuo-Hsiang Chou Sent: Wednesday, May 26, 2021 6:24 PM To: tzimmermann@suse.de; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org Subject: RE: [PATCH v4] drm/ast: Disable fast reset after DRAM initial -----Original Message----- From: Kuo-Hsiang Chou Sent: Friday, May 07, 2021 5:27 PM To: tzimmermann@suse.de; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org Cc: airlied@redhat.com; airlied@linux.ie; daniel@ffwll.ch; Jenmin Yuan <jenmin_yuan@aspeedtech.com>; Kuo-Hsiang Chou <kuohsiang_chou@aspeedtech.com>; Arc Sung <arc_sung@aspeedtech.com> Subject: [PATCH v4] drm/ast: Disable fast reset after DRAM initial Hi Thomas, May I know if this patch has sth wrong. Or something I need to improve on it, I can fix it right now. Thanks! Regards, Kuo-Hsiang Chou [Bug][AST2500] V1: When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization have to be achieved by VGA driver with P2A (PCI to AHB) enabling. However, HW suggests disable Fast reset mode after DRAM initializaton, because fast reset mode is mainly designed for ARM ICE debugger. Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be first enabled to avoid system deadlock before disable fast reset mode. V2: Use to_pci_dev() to get revision of PCI configuration. V3: If SCU00 is not unlocked, just enter its password again. It is unnecessary to clear AHB lock condition and restore WDT default setting again, before Fast-reset clearing. V4: repatch after "error : could not build fake ancestor" resolved. Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> --- drivers/gpu/drm/ast/ast_drv.h | 1 + drivers/gpu/drm/ast/ast_main.c | 4 ++ drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++------------- 3 files changed, 47 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 911f9f414..5ebb5905d 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -346,6 +346,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); +void ast_patch_ahb_2500(struct ast_private *ast); /* ast dp501 */ void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 2aff2e6cf..cfb56ea3a 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -97,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Patch AST2500 */ + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) + ast_patch_ahb_2500(ast); + /* Double check it's actually working */ data = ast_read32(ast, 0xf004); if ((data != 0xFFFFFFFF) && (data != 0x00)) { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 0607658dd..56428798a 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -2028,6 +2028,30 @@ static bool ast_dram_init_2500(struct ast_private *ast) return true; } +void ast_patch_ahb_2500(struct ast_private *ast) { + u32 data; + + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2070); + if (data & 0x08000000) { /* check fast reset */ + + ast_moutdwm(ast, 0x1E785004, 0x00000010); + ast_moutdwm(ast, 0x1E785008, 0x00004755); + ast_moutdwm(ast, 0x1E78500c, 0x00000033); + udelay(1000); + } + do { + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2000); + } while (data != 1); + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ +} + void ast_post_chip_2500(struct drm_device *dev) { struct ast_private *ast = to_ast_private(dev); @@ -2035,39 +2059,31 @@ void ast_post_chip_2500(struct drm_device *dev) u8 reg; reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); - if ((reg & 0x80) == 0) {/* vga only */ + if ((reg & 0xC0) == 0) {/* vga only */ /* Clear bus lock condition */ - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); - ast_moutdwm(ast, 0x1e600084, 0x00010000); - ast_moutdwm(ast, 0x1e600088, 0x00000000); - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); - while (ast_read32(ast, 0x12000) != 0x1) - ; - - ast_write32(ast, 0x10000, 0xfc600309); - while (ast_read32(ast, 0x10000) != 0x1) - ; + ast_patch_ahb_2500(ast); + + /* Disable watchdog */ + ast_moutdwm(ast, 0x1E78502C, 0x00000000); + ast_moutdwm(ast, 0x1E78504C, 0x00000000); + /* Reset USB port */ + ast_moutdwm(ast, 0x1E6E2090, 0x20000000); + ast_moutdwm(ast, 0x1E6E2094, 0x00004000); + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { + ast_moutdwm(ast, 0x1E6E207C, 0x00800000); + mdelay(100); + ast_moutdwm(ast, 0x1E6E2070, 0x00800000); + } + /* Modify eSPI reset pin */ + temp = ast_mindwm(ast, 0x1E6E2070); + if (temp & 0x02000000) + ast_moutdwm(ast, 0x1E6E207C, 0x00004000); /* Slow down CPU/AHB CLK in VGA only mode */ temp = ast_read32(ast, 0x12008); temp |= 0x73; ast_write32(ast, 0x12008, temp); - /* Reset USB port to patch USB unknown device issue */ - ast_moutdwm(ast, 0x1e6e2090, 0x20000000); - temp = ast_mindwm(ast, 0x1e6e2094); - temp |= 0x00004000; - ast_moutdwm(ast, 0x1e6e2094, temp); - temp = ast_mindwm(ast, 0x1e6e2070); - if (temp & 0x00800000) { - ast_moutdwm(ast, 0x1e6e207c, 0x00800000); - mdelay(100); - ast_moutdwm(ast, 0x1e6e2070, 0x00800000); - } - if (!ast_dram_init_2500(ast)) drm_err(dev, "DRAM init failed !\n"); -- 2.18.4
Hi Am 21.06.21 um 13:06 schrieb Kuo-Hsiang Chou: > Hi Thomas, > > May I know if I need to port this patch to the latest drm-misc-next again, because the patch has send to review for a while. > If the porting or any other thing can reduce your review effort, please instruct me. Thanks! I'm sorry for not replying to you. I've been away for a while and had limited time. I only returned to work today and will look at the patch soon. Best regards Thomas > > Best Regards, > Kuo-Hsiang Chou > > -----Original Message----- > From: dri-devel [mailto:dri-devel-bounces@lists.freedesktop.org] On Behalf Of Kuo-Hsiang Chou > Sent: Wednesday, May 26, 2021 6:24 PM > To: tzimmermann@suse.de; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org > Subject: RE: [PATCH v4] drm/ast: Disable fast reset after DRAM initial > > > > -----Original Message----- > From: Kuo-Hsiang Chou > Sent: Friday, May 07, 2021 5:27 PM > To: tzimmermann@suse.de; dri-devel@lists.freedesktop.org; linux-kernel@vger.kernel.org > Cc: airlied@redhat.com; airlied@linux.ie; daniel@ffwll.ch; Jenmin Yuan <jenmin_yuan@aspeedtech.com>; Kuo-Hsiang Chou <kuohsiang_chou@aspeedtech.com>; Arc Sung <arc_sung@aspeedtech.com> > Subject: [PATCH v4] drm/ast: Disable fast reset after DRAM initial > > Hi Thomas, > > May I know if this patch has sth wrong. Or something I need to improve on it, I can fix it right now. Thanks! > > Regards, > Kuo-Hsiang Chou > > [Bug][AST2500] > > V1: > When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization have to be achieved by VGA driver with P2A (PCI to AHB) enabling. > However, HW suggests disable Fast reset mode after DRAM initializaton, because fast reset mode is mainly designed for ARM ICE debugger. > Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be first enabled to avoid system deadlock before disable fast reset mode. > > V2: > Use to_pci_dev() to get revision of PCI configuration. > > V3: > If SCU00 is not unlocked, just enter its password again. > It is unnecessary to clear AHB lock condition and restore WDT default setting again, before Fast-reset clearing. > > V4: > repatch after "error : could not build fake ancestor" resolved. > > Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> > --- > drivers/gpu/drm/ast/ast_drv.h | 1 + > drivers/gpu/drm/ast/ast_main.c | 4 ++ > drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++------------- > 3 files changed, 47 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 911f9f414..5ebb5905d 100644 > --- a/drivers/gpu/drm/ast/ast_drv.h > +++ b/drivers/gpu/drm/ast/ast_drv.h > @@ -346,6 +346,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); > u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); > +void ast_patch_ahb_2500(struct ast_private *ast); > /* ast dp501 */ > void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 2aff2e6cf..cfb56ea3a 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -97,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) > jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); > jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); > if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { > + /* Patch AST2500 */ > + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) > + ast_patch_ahb_2500(ast); > + > /* Double check it's actually working */ > data = ast_read32(ast, 0xf004); > if ((data != 0xFFFFFFFF) && (data != 0x00)) { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 0607658dd..56428798a 100644 > --- a/drivers/gpu/drm/ast/ast_post.c > +++ b/drivers/gpu/drm/ast/ast_post.c > @@ -2028,6 +2028,30 @@ static bool ast_dram_init_2500(struct ast_private *ast) > return true; > } > > +void ast_patch_ahb_2500(struct ast_private *ast) { > + u32 data; > + > + /* Clear bus lock condition */ > + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); > + ast_moutdwm(ast, 0x1e600084, 0x00010000); > + ast_moutdwm(ast, 0x1e600088, 0x00000000); > + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > + data = ast_mindwm(ast, 0x1e6e2070); > + if (data & 0x08000000) { /* check fast reset */ > + > + ast_moutdwm(ast, 0x1E785004, 0x00000010); > + ast_moutdwm(ast, 0x1E785008, 0x00004755); > + ast_moutdwm(ast, 0x1E78500c, 0x00000033); > + udelay(1000); > + } > + do { > + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > + data = ast_mindwm(ast, 0x1e6e2000); > + } while (data != 1); > + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ > +} > + > void ast_post_chip_2500(struct drm_device *dev) { > struct ast_private *ast = to_ast_private(dev); @@ -2035,39 +2059,31 @@ void ast_post_chip_2500(struct drm_device *dev) > u8 reg; > > reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); > - if ((reg & 0x80) == 0) {/* vga only */ > + if ((reg & 0xC0) == 0) {/* vga only */ > /* Clear bus lock condition */ > - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); > - ast_moutdwm(ast, 0x1e600084, 0x00010000); > - ast_moutdwm(ast, 0x1e600088, 0x00000000); > - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > - ast_write32(ast, 0xf004, 0x1e6e0000); > - ast_write32(ast, 0xf000, 0x1); > - ast_write32(ast, 0x12000, 0x1688a8a8); > - while (ast_read32(ast, 0x12000) != 0x1) > - ; > - > - ast_write32(ast, 0x10000, 0xfc600309); > - while (ast_read32(ast, 0x10000) != 0x1) > - ; > + ast_patch_ahb_2500(ast); > + > + /* Disable watchdog */ > + ast_moutdwm(ast, 0x1E78502C, 0x00000000); > + ast_moutdwm(ast, 0x1E78504C, 0x00000000); > + /* Reset USB port */ > + ast_moutdwm(ast, 0x1E6E2090, 0x20000000); > + ast_moutdwm(ast, 0x1E6E2094, 0x00004000); > + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { > + ast_moutdwm(ast, 0x1E6E207C, 0x00800000); > + mdelay(100); > + ast_moutdwm(ast, 0x1E6E2070, 0x00800000); > + } > + /* Modify eSPI reset pin */ > + temp = ast_mindwm(ast, 0x1E6E2070); > + if (temp & 0x02000000) > + ast_moutdwm(ast, 0x1E6E207C, 0x00004000); > > /* Slow down CPU/AHB CLK in VGA only mode */ > temp = ast_read32(ast, 0x12008); > temp |= 0x73; > ast_write32(ast, 0x12008, temp); > > - /* Reset USB port to patch USB unknown device issue */ > - ast_moutdwm(ast, 0x1e6e2090, 0x20000000); > - temp = ast_mindwm(ast, 0x1e6e2094); > - temp |= 0x00004000; > - ast_moutdwm(ast, 0x1e6e2094, temp); > - temp = ast_mindwm(ast, 0x1e6e2070); > - if (temp & 0x00800000) { > - ast_moutdwm(ast, 0x1e6e207c, 0x00800000); > - mdelay(100); > - ast_moutdwm(ast, 0x1e6e2070, 0x00800000); > - } > - > if (!ast_dram_init_2500(ast)) > drm_err(dev, "DRAM init failed !\n"); > > -- > 2.18.4 >
Hi, here's the review that you've been waiting for. Sorry for taking so long. Am 07.05.21 um 11:27 schrieb KuoHsiang Chou: > [Bug][AST2500] > > V1: > When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization > have to be achieved by VGA driver with P2A (PCI to AHB) enabling. > However, HW suggests disable Fast reset mode after DRAM initializaton, > because fast reset mode is mainly designed for ARM ICE debugger. > Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be > first enabled to avoid system deadlock before disable fast reset mode. > > V2: > Use to_pci_dev() to get revision of PCI configuration. > > V3: > If SCU00 is not unlocked, just enter its password again. > It is unnecessary to clear AHB lock condition and restore WDT default > setting again, before Fast-reset clearing. > > V4: > repatch after "error : could not build fake ancestor" resolved. > > Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> > --- > drivers/gpu/drm/ast/ast_drv.h | 1 + > drivers/gpu/drm/ast/ast_main.c | 4 ++ > drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++------------- > 3 files changed, 47 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h > index 911f9f414..5ebb5905d 100644 > --- a/drivers/gpu/drm/ast/ast_drv.h > +++ b/drivers/gpu/drm/ast/ast_drv.h > @@ -346,6 +346,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); > void ast_post_gpu(struct drm_device *dev); > u32 ast_mindwm(struct ast_private *ast, u32 r); > void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); > +void ast_patch_ahb_2500(struct ast_private *ast); > /* ast dp501 */ > void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); > bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index 2aff2e6cf..cfb56ea3a 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -97,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) > jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); > jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); > if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { > + /* Patch AST2500 */ > + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) These magic numbers are hard to read. Is there any way of make it more clear what we're testing for? Constants? Helper functions? > + ast_patch_ahb_2500(ast); > + > /* Double check it's actually working */ > data = ast_read32(ast, 0xf004); > if ((data != 0xFFFFFFFF) && (data != 0x00)) { > diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c > index 0607658dd..56428798a 100644 > --- a/drivers/gpu/drm/ast/ast_post.c > +++ b/drivers/gpu/drm/ast/ast_post.c > @@ -2028,6 +2028,30 @@ static bool ast_dram_init_2500(struct ast_private *ast) > return true; > } > > +void ast_patch_ahb_2500(struct ast_private *ast) > +{ > + u32 data; Only a single space after the type. > + > + /* Clear bus lock condition */ > + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); > + ast_moutdwm(ast, 0x1e600084, 0x00010000); > + ast_moutdwm(ast, 0x1e600088, 0x00000000); > + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > + data = ast_mindwm(ast, 0x1e6e2070); > + if (data & 0x08000000) { /* check fast reset */ > + No empty line here. > + ast_moutdwm(ast, 0x1E785004, 0x00000010); > + ast_moutdwm(ast, 0x1E785008, 0x00004755); > + ast_moutdwm(ast, 0x1E78500c, 0x00000033); > + udelay(1000); > + } > + do { > + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > + data = ast_mindwm(ast, 0x1e6e2000); > + } while (data != 1); > + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ > +} > + > void ast_post_chip_2500(struct drm_device *dev) > { > struct ast_private *ast = to_ast_private(dev); > @@ -2035,39 +2059,31 @@ void ast_post_chip_2500(struct drm_device *dev) > u8 reg; > > reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); > - if ((reg & 0x80) == 0) {/* vga only */ > + if ((reg & 0xC0) == 0) {/* vga only */ Why this change? > /* Clear bus lock condition */ > - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); > - ast_moutdwm(ast, 0x1e600084, 0x00010000); > - ast_moutdwm(ast, 0x1e600088, 0x00000000); > - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); > - ast_write32(ast, 0xf004, 0x1e6e0000); > - ast_write32(ast, 0xf000, 0x1); > - ast_write32(ast, 0x12000, 0x1688a8a8); > - while (ast_read32(ast, 0x12000) != 0x1) > - ; > - > - ast_write32(ast, 0x10000, 0xfc600309); > - while (ast_read32(ast, 0x10000) != 0x1) > - ; > + ast_patch_ahb_2500(ast); You're calling this function here, but it's different from the old code. > + > + /* Disable watchdog */ > + ast_moutdwm(ast, 0x1E78502C, 0x00000000); > + ast_moutdwm(ast, 0x1E78504C, 0x00000000); > + /* Reset USB port */ Reset USB port? In the graphics driver? The whole gpu post/init code is undecipherable to me. It's full of magic numbers that are nowhere documented. Therefore, the overall problem with this patch is that I have no idea what the actual bug fix is. Is it possible to first refactor that code a bit and then add a minimal fix? Best regards Thomas
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index 911f9f414..5ebb5905d 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -346,6 +346,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); +void ast_patch_ahb_2500(struct ast_private *ast); /* ast dp501 */ void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 2aff2e6cf..cfb56ea3a 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -97,6 +97,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Patch AST2500 */ + if (((pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) + ast_patch_ahb_2500(ast); + /* Double check it's actually working */ data = ast_read32(ast, 0xf004); if ((data != 0xFFFFFFFF) && (data != 0x00)) { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 0607658dd..56428798a 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -2028,6 +2028,30 @@ static bool ast_dram_init_2500(struct ast_private *ast) return true; } +void ast_patch_ahb_2500(struct ast_private *ast) +{ + u32 data; + + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2070); + if (data & 0x08000000) { /* check fast reset */ + + ast_moutdwm(ast, 0x1E785004, 0x00000010); + ast_moutdwm(ast, 0x1E785008, 0x00004755); + ast_moutdwm(ast, 0x1E78500c, 0x00000033); + udelay(1000); + } + do { + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2000); + } while (data != 1); + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ +} + void ast_post_chip_2500(struct drm_device *dev) { struct ast_private *ast = to_ast_private(dev); @@ -2035,39 +2059,31 @@ void ast_post_chip_2500(struct drm_device *dev) u8 reg; reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); - if ((reg & 0x80) == 0) {/* vga only */ + if ((reg & 0xC0) == 0) {/* vga only */ /* Clear bus lock condition */ - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); - ast_moutdwm(ast, 0x1e600084, 0x00010000); - ast_moutdwm(ast, 0x1e600088, 0x00000000); - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); - while (ast_read32(ast, 0x12000) != 0x1) - ; - - ast_write32(ast, 0x10000, 0xfc600309); - while (ast_read32(ast, 0x10000) != 0x1) - ; + ast_patch_ahb_2500(ast); + + /* Disable watchdog */ + ast_moutdwm(ast, 0x1E78502C, 0x00000000); + ast_moutdwm(ast, 0x1E78504C, 0x00000000); + /* Reset USB port */ + ast_moutdwm(ast, 0x1E6E2090, 0x20000000); + ast_moutdwm(ast, 0x1E6E2094, 0x00004000); + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { + ast_moutdwm(ast, 0x1E6E207C, 0x00800000); + mdelay(100); + ast_moutdwm(ast, 0x1E6E2070, 0x00800000); + } + /* Modify eSPI reset pin */ + temp = ast_mindwm(ast, 0x1E6E2070); + if (temp & 0x02000000) + ast_moutdwm(ast, 0x1E6E207C, 0x00004000); /* Slow down CPU/AHB CLK in VGA only mode */ temp = ast_read32(ast, 0x12008); temp |= 0x73; ast_write32(ast, 0x12008, temp); - /* Reset USB port to patch USB unknown device issue */ - ast_moutdwm(ast, 0x1e6e2090, 0x20000000); - temp = ast_mindwm(ast, 0x1e6e2094); - temp |= 0x00004000; - ast_moutdwm(ast, 0x1e6e2094, temp); - temp = ast_mindwm(ast, 0x1e6e2070); - if (temp & 0x00800000) { - ast_moutdwm(ast, 0x1e6e207c, 0x00800000); - mdelay(100); - ast_moutdwm(ast, 0x1e6e2070, 0x00800000); - } - if (!ast_dram_init_2500(ast)) drm_err(dev, "DRAM init failed !\n");
[Bug][AST2500] V1: When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization have to be achieved by VGA driver with P2A (PCI to AHB) enabling. However, HW suggests disable Fast reset mode after DRAM initializaton, because fast reset mode is mainly designed for ARM ICE debugger. Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be first enabled to avoid system deadlock before disable fast reset mode. V2: Use to_pci_dev() to get revision of PCI configuration. V3: If SCU00 is not unlocked, just enter its password again. It is unnecessary to clear AHB lock condition and restore WDT default setting again, before Fast-reset clearing. V4: repatch after "error : could not build fake ancestor" resolved. Signed-off-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com> --- drivers/gpu/drm/ast/ast_drv.h | 1 + drivers/gpu/drm/ast/ast_main.c | 4 ++ drivers/gpu/drm/ast/ast_post.c | 68 +++++++++++++++++++++------------- 3 files changed, 47 insertions(+), 26 deletions(-) -- 2.18.4