| Message ID | 20210513171431.18632-9-jonathan@marek.ca (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm/a6xx: add support for Adreno 660 GPU | expand |
On 5/13/2021 10:44 PM, Jonathan Marek wrote: > Add a660 hwcg table, ported over from downstream. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- > 3 files changed, 55 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index ec66a24fc37e..2713f69e916d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { > {}, > }; > > +const struct adreno_reglist a660_hwcg[] = { > + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, > + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, > + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, > + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, > + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, > + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, > + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, > + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, > + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, > + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, > + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, > + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, > + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, > + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, > + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, > + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, > + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, > + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, > + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, > + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, > + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, > + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, > + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, > + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, > + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, > + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, > + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, > + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, > + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, > + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, > + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, > + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, > + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, > + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, > + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, > + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, > + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, > + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, > + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, > + {}, > +}; > + > static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index e4db0683d381..6dad8015c9a1 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -299,6 +299,7 @@ static const struct adreno_info gpulist[] = { > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > .init = a6xx_gpu_init, > .zapfw = "a660_zap.mdt", > + .hwcg = a660_hwcg, > }, > }; > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 63c050919d85..e6b11e6ec82d 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -55,7 +55,7 @@ struct adreno_reglist { > u32 value; > }; > > -extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[]; > +extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; > > struct adreno_info { > struct adreno_rev rev; > squash with previous one? -Akhil
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index ec66a24fc37e..2713f69e916d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { {}, }; +const struct adreno_reglist a660_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e4db0683d381..6dad8015c9a1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -299,6 +299,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", + .hwcg = a660_hwcg, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 63c050919d85..e6b11e6ec82d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,7 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; struct adreno_info { struct adreno_rev rev;
Add a660 hwcg table, ported over from downstream. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- 3 files changed, 55 insertions(+), 1 deletion(-)