From patchwork Tue Jun 1 10:41:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 12290933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F9CC47092 for ; Tue, 1 Jun 2021 10:06:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23CF961370 for ; Tue, 1 Jun 2021 10:06:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23CF961370 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F5576E9D4; Tue, 1 Jun 2021 10:06:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1638C6E9DE; Tue, 1 Jun 2021 10:06:03 +0000 (UTC) IronPort-SDR: 3bGnSxKDRG8wRYpbL8Gr57YHiDcLRpB6BscGK4tPCsx64GSAOt6P0m4r2PobgWixVr1vSAcBJD pE69eoZjK3zA== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="183197776" X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="183197776" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:06:01 -0700 IronPort-SDR: nAMCoBFdy5aRuUvxZGNXIUYlF7/TEDzuXVuVdXHIkhqzlAbPQPRmcwM2u0+Ej9pCok3rF6az2v GHHo6Gw2vBVA== X-IronPort-AV: E=Sophos;i="5.83,239,1616482800"; d="scan'208";a="399245279" Received: from linux-desktop.iind.intel.com ([10.223.34.178]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2021 03:05:59 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout Date: Tue, 1 Jun 2021 16:11:35 +0530 Message-Id: <20210601104135.29020-10-uma.shankar@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210601104135.29020-1-uma.shankar@intel.com> References: <20210601104135.29020-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , bhanuprakash.modem@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable support for Logarithmic gamma readout for XE_LPD. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a8b771f22880..1238fe05b358 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw); } +static void d13_lut_logarithmic_pack(struct drm_color_lut *entry, + u32 ldw, u32 udw) +{ + entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw); + entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw); + entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 | + REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw); +} + static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state) intel_dsb_commit(crtc_state); } +static struct drm_property_blob * +d13_read_lut_logarithmic(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + u32 gamma_max_val = 0xFFFF; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * lut_size, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size - 3; i++) { + u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + + d13_lut_logarithmic_pack(&lut[i], ldw, udw); + } + + /* All the extended ranges are now limited to last value of 1.0 */ + while (i < lut_size) { + lut[i].red = gamma_max_val; + lut[i].green = gamma_max_val; + lut[i].blue = gamma_max_val; + i++; + }; + + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); + + return blob; +} + +static void d13_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0) + return; + + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { + case GAMMA_MODE_MODE_8BIT: + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_12BIT_LOGARITHMIC: + crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc); + break; + default: + crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + } +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc) if (DISPLAY_VER(dev_priv) >= 13) { dev_priv->display.load_luts = d13_load_luts; + dev_priv->display.read_luts = d13_read_luts; } else if (DISPLAY_VER(dev_priv) >= 11) { dev_priv->display.load_luts = icl_load_luts; dev_priv->display.read_luts = icl_read_luts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 957f97edf035..dc10b5e2ff3c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7750,6 +7750,12 @@ enum { #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ #define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */ +#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24) +#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20) +#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4) +#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0) /* DMC */ #define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)