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[1/7] drm/msm: Don't break exclusive fence ordering

Message ID 20210706101209.3034092-2-daniel.vetter@ffwll.ch (mailing list archive)
State New, archived
Headers show
Series dma-resv fence DAG fixes | expand

Commit Message

Daniel Vetter July 6, 2021, 10:12 a.m. UTC
There's only one exclusive slot, and we must not break the ordering.

A better fix would be to us a dma_fence_chain or _array like e.g.
amdgpu now uses, but
- msm has a synchronous dma_fence_wait for anything from another
  context, so doesn't seem to care much,
- and it probably makes sense to lift this into dma-resv.c code as a
  proper concept, so that drivers don't have to hack up their own
  solution each on their own.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
 drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series


diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c
index b71da71a3dd8..edd0051d849f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -306,7 +306,8 @@  static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
 				return ret;
-		if (no_implicit)
+		/* exclusive fences must be ordered */
+		if (no_implicit && !write)
 		ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx,