From patchwork Mon Jul 12 17:53:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 12372213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D963CC11F68 for ; Mon, 12 Jul 2021 20:02:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2397611F1 for ; Mon, 12 Jul 2021 20:02:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2397611F1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ffwll.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9839D89DBC; Mon, 12 Jul 2021 20:02:02 +0000 (UTC) Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 424DF89DB2 for ; Mon, 12 Jul 2021 20:02:01 +0000 (UTC) Received: by mail-wm1-x32a.google.com with SMTP id y21-20020a7bc1950000b02902161fccabf1so20148wmi.2 for ; Mon, 12 Jul 2021 13:02:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GSY9W1VxCdMpypdkbaup7CixlFsk0s/gKk3ObtLJVLg=; b=XrD3D9ja9dBSoDlgsVH+He3M/Qnc0g7g5V9iYxxuxX6OVy1Ym1kO5KoUk40/N1BN73 23PWAIQLn4cpJJ9jvhn+wPxhgbHvmtvGhRn+nF/fMXvrF3HJu8+SgkN0eEO0TGvc3Qz4 UUPaQKOpnGzWXy5tRBYl/sEyZTfWKZTVZ3wVQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GSY9W1VxCdMpypdkbaup7CixlFsk0s/gKk3ObtLJVLg=; b=VABP7sSCuPbuuLZlh+efCYCe+FJTUjyoP70XFFGVDrmowzE0+SeCGd7KC5K1FtpZTG Ia9FID6zRdLiTTbwAFL6Cl6FAgLTjT7U/nlswcEnVfgZdNwfRcttLLfzIdnzV+4NtESC xKbOc0RO4s/JKNDLAmrROB3Rg8703PGRQddYoyxBcazvrSIPSFVhCfiYDDMe2PORXe1m JVxa/xZU570mVCjopcr3LSFEmFGB1Ib2P06KUOtW/mmsRE/2+pMtVDNqKnNtB+GWRKfl gwAhjTIfT03EA+iCKLY/YVt/uM8r84MeWtJn14ljWnU9zApoQoReNHXVSdEn2we0SUBU dx1A== X-Gm-Message-State: AOAM5322PYM+FcxL3shesbimSjh0GHUE5697eDOOEDfRIKGyoIdmYO5U x/sHr+sQruPgbd9fQmRb4Y6Pc/78sHof4w== X-Google-Smtp-Source: ABdhPJxjeXPggqYsDGc4BnsH9bBPwkFEgfpctPnYSmhVAPacjN8G/a6BByHv1WYSDK7vT2aFCPkqAA== X-Received: by 2002:a1c:9dd6:: with SMTP id g205mr959206wme.82.1626120119757; Mon, 12 Jul 2021 13:01:59 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id l14sm9858221wrs.22.2021.07.12.13.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 13:01:59 -0700 (PDT) From: Daniel Vetter To: DRI Development Subject: [PATCH v4 02/18] drm/sched: Barriers are needed for entity->last_scheduled Date: Mon, 12 Jul 2021 19:53:36 +0200 Message-Id: <20210712175352.802687-3-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210712175352.802687-1-daniel.vetter@ffwll.ch> References: <20210712175352.802687-1-daniel.vetter@ffwll.ch> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , Intel Graphics Development , Steven Price , Boris Brezillon , Daniel Vetter , Lee Jones , =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It might be good enough on x86 with just READ_ONCE, but the write side should then at least be WRITE_ONCE because x86 has total store order. It's definitely not enough on arm. Fix this proplery, which means - explain the need for the barrier in both places - point at the other side in each comment Also pull out the !sched_list case as the first check, so that the code flow is clearer. While at it sprinkle some comments around because it was very non-obvious to me what's actually going on here and why. Note that we really need full barriers here, at first I thought store-release and load-acquire on ->last_scheduled would be enough, but we actually requiring ordering between that and the queue state. v2: Put smp_rmp() in the right place and fix up comment (Andrey) Signed-off-by: Daniel Vetter Cc: "Christian König" Cc: Steven Price Cc: Daniel Vetter Cc: Andrey Grodzovsky Cc: Lee Jones Cc: Boris Brezillon --- drivers/gpu/drm/scheduler/sched_entity.c | 27 ++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index f7347c284886..89e3f6eaf519 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -439,8 +439,16 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) dma_fence_set_error(&sched_job->s_fence->finished, -ECANCELED); dma_fence_put(entity->last_scheduled); + entity->last_scheduled = dma_fence_get(&sched_job->s_fence->finished); + /* + * If the queue is empty we allow drm_sched_entity_select_rq() to + * locklessly access ->last_scheduled. This only works if we set the + * pointer before we dequeue and if we a write barrier here. + */ + smp_wmb(); + spsc_queue_pop(&entity->job_queue); return sched_job; } @@ -459,10 +467,25 @@ void drm_sched_entity_select_rq(struct drm_sched_entity *entity) struct drm_gpu_scheduler *sched; struct drm_sched_rq *rq; - if (spsc_queue_count(&entity->job_queue) || !entity->sched_list) + /* single possible engine and already selected */ + if (!entity->sched_list) + return; + + /* queue non-empty, stay on the same engine */ + if (spsc_queue_count(&entity->job_queue)) return; - fence = READ_ONCE(entity->last_scheduled); + /* + * Only when the queue is empty are we guaranteed that the scheduler + * thread cannot change ->last_scheduled. To enforce ordering we need + * a read barrier here. See drm_sched_entity_pop_job() for the other + * side. + */ + smp_rmb(); + + fence = entity->last_scheduled; + + /* stay on the same engine if the previous job hasn't finished */ if (fence && !dma_fence_is_signaled(fence)) return;