| Message ID | 20210910053317.3379249-2-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i915: Simplify mmio handling & add new DG2 shadow table | expand |
On 10/09/2021 06:33, Matt Roper wrote: > On gen6-gen8 (except vlv/chv) we don't use a forcewake lookup table; we > simply check whether the register offset is < 0x40000, and return > FORCEWAKE_RENDER if it is. To prepare for upcoming refactoring, let's > define a single-entry forcewake table from [0x0, 0x3ffff] and switch > these platforms over to use the fwtable reader functions. > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index f9767054dbdf..7f92f12d95f2 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1064,6 +1064,10 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) > __fwd; \ > }) > Is __gen6_reg_read_fw_domains left orphaned somewhere around here or in a later patch? Regards, Tvrtko > +static const struct intel_forcewake_range __gen6_fw_ranges[] = { > + GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER), > +}; > + > /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ > static const struct intel_forcewake_range __chv_fw_ranges[] = { > GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), > @@ -1623,7 +1627,6 @@ __gen_read(func, 64) > > __gen_reg_read_funcs(gen11_fwtable); > __gen_reg_read_funcs(fwtable); > -__gen_reg_read_funcs(gen6); > > #undef __gen_reg_read_funcs > #undef GEN6_READ_FOOTER > @@ -2111,15 +2114,17 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) > ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); > ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); > } else if (GRAPHICS_VER(i915) == 8) { > + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); > - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); > + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); > } else if (IS_VALLEYVIEW(i915)) { > ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); > ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); > } else if (IS_GRAPHICS_VER(i915, 6, 7)) { > + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); > - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); > + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); > } > > uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; >
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f9767054dbdf..7f92f12d95f2 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1064,6 +1064,10 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) __fwd; \ }) +static const struct intel_forcewake_range __gen6_fw_ranges[] = { + GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER), +}; + /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ static const struct intel_forcewake_range __chv_fw_ranges[] = { GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), @@ -1623,7 +1627,6 @@ __gen_read(func, 64) __gen_reg_read_funcs(gen11_fwtable); __gen_reg_read_funcs(fwtable); -__gen_reg_read_funcs(gen6); #undef __gen_reg_read_funcs #undef GEN6_READ_FOOTER @@ -2111,15 +2114,17 @@ static int uncore_forcewake_init(struct intel_uncore *uncore) ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); } else if (GRAPHICS_VER(i915) == 8) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); } else if (IS_VALLEYVIEW(i915)) { ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); } else if (IS_GRAPHICS_VER(i915, 6, 7)) { + ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); - ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); + ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); } uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
On gen6-gen8 (except vlv/chv) we don't use a forcewake lookup table; we simply check whether the register offset is < 0x40000, and return FORCEWAKE_RENDER if it is. To prepare for upcoming refactoring, let's define a single-entry forcewake table from [0x0, 0x3ffff] and switch these platforms over to use the fwtable reader functions. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)