diff mbox series

[v2,5/6] drm/i915/uncore: Drop gen11 mmio read handlers

Message ID 20210910201030.3436066-6-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: Simplify mmio handling & add new DG2 shadow table | expand

Commit Message

Matt Roper Sept. 10, 2021, 8:10 p.m. UTC 
Consolidate down to just a single 'fwtable' implementation.  For reads
we don't need to worry about shadow tables.  Also, the
NEEDS_FORCE_WAKE() check we previously had in the fwtable implementation
can be dropped --- if a register is outside that range on one of the old
platforms, then it won't belong to any forcewake range and 0 will be
returned anyway.

v2:
 - Restore NEEDS_FORCE_WAKE() check.  (Chris, Tvrtko)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 40 ++++++++++++-----------------
 1 file changed, 17 insertions(+), 23 deletions(-)

Comments

Tvrtko Ursulin Sept. 21, 2021, 2:40 p.m. UTC | #1 
On 10/09/2021 21:10, Matt Roper wrote:
> Consolidate down to just a single 'fwtable' implementation.  For reads
> we don't need to worry about shadow tables.  Also, the
> NEEDS_FORCE_WAKE() check we previously had in the fwtable implementation
> can be dropped --- if a register is outside that range on one of the old
> platforms, then it won't belong to any forcewake range and 0 will be
> returned anyway.
> 
> v2:
>   - Restore NEEDS_FORCE_WAKE() check.  (Chris, Tvrtko)

I started liking rewording the commit message when the revision log 
starts contradicting it, but it is just a suggestion.

> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_uncore.c | 40 ++++++++++++-----------------
>   1 file changed, 17 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index bfb2a6337f9d..10f124297e7c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -935,9 +935,6 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
>   	__fwd; \
>   })
>   
> -#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
> -	find_fw_domain(uncore, offset)
> -
>   /* *Must* be sorted by offset! See intel_shadow_table_check(). */
>   static const struct i915_range gen8_shadowed_regs[] = {
>   	{ .start =  0x2030, .end =  0x2030 },
> @@ -1570,33 +1567,30 @@ static inline void __force_wake_auto(struct intel_uncore *uncore,
>   		___force_wake_auto(uncore, fw_domains);
>   }
>   
> -#define __gen_read(func, x) \
> +#define __gen_fwtable_read(x) \
>   static u##x \
> -func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
> +fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
> +{ \
>   	enum forcewake_domains fw_engine; \
>   	GEN6_READ_HEADER(x); \
> -	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
> +	fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
>   	if (fw_engine) \
>   		__force_wake_auto(uncore, fw_engine); \
>   	val = __raw_uncore_read##x(uncore, reg); \
>   	GEN6_READ_FOOTER; \
>   }
>   
> -#define __gen_reg_read_funcs(func) \
> -static enum forcewake_domains \
> -func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
> -	return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
> -} \
> -\
> -__gen_read(func, 8) \
> -__gen_read(func, 16) \
> -__gen_read(func, 32) \
> -__gen_read(func, 64)
> +static enum forcewake_domains
> +fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
> +	return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
> +}
>   
> -__gen_reg_read_funcs(gen11_fwtable);
> -__gen_reg_read_funcs(fwtable);
> +__gen_fwtable_read(8)
> +__gen_fwtable_read(16)
> +__gen_fwtable_read(32)
> +__gen_fwtable_read(64)
>   
> -#undef __gen_reg_read_funcs
> +#undef __gen_fwtable_read
>   #undef GEN6_READ_FOOTER
>   #undef GEN6_READ_HEADER
>   
> @@ -2062,22 +2056,22 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
>   		ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
>   		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>   		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> -		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> +		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
>   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>   		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
>   		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>   		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> -		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> +		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
>   	} else if (GRAPHICS_VER(i915) >= 12) {
>   		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
>   		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
>   		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> -		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> +		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
>   	} else if (GRAPHICS_VER(i915) == 11) {
>   		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
>   		ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
>   		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> -		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> +		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
>   	} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
>   		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
>   		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
Lucas De Marchi Sept. 21, 2021, 5:36 p.m. UTC | #2 
On Fri, Sep 10, 2021 at 01:10:29PM -0700, Matt Roper wrote:
>Consolidate down to just a single 'fwtable' implementation.  For reads
>we don't need to worry about shadow tables.  Also, the
>NEEDS_FORCE_WAKE() check we previously had in the fwtable implementation
>can be dropped --- if a register is outside that range on one of the old
>platforms, then it won't belong to any forcewake range and 0 will be
>returned anyway.
>
>v2:
> - Restore NEEDS_FORCE_WAKE() check.  (Chris, Tvrtko)
>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/intel_uncore.c | 40 ++++++++++++-----------------
> 1 file changed, 17 insertions(+), 23 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>index bfb2a6337f9d..10f124297e7c 100644
>--- a/drivers/gpu/drm/i915/intel_uncore.c
>+++ b/drivers/gpu/drm/i915/intel_uncore.c
>@@ -935,9 +935,6 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
> 	__fwd; \
> })
>
>-#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
>-	find_fw_domain(uncore, offset)
>-
> /* *Must* be sorted by offset! See intel_shadow_table_check(). */
> static const struct i915_range gen8_shadowed_regs[] = {
> 	{ .start =  0x2030, .end =  0x2030 },
>@@ -1570,33 +1567,30 @@ static inline void __force_wake_auto(struct intel_uncore *uncore,
> 		___force_wake_auto(uncore, fw_domains);
> }
>
>-#define __gen_read(func, x) \
>+#define __gen_fwtable_read(x) \
> static u##x \
>-func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
>+fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
>+{ \
> 	enum forcewake_domains fw_engine; \
> 	GEN6_READ_HEADER(x); \
>-	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
>+	fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
> 	if (fw_engine) \
> 		__force_wake_auto(uncore, fw_engine); \
> 	val = __raw_uncore_read##x(uncore, reg); \
> 	GEN6_READ_FOOTER; \
> }
>
>-#define __gen_reg_read_funcs(func) \
>-static enum forcewake_domains \
>-func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
>-	return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
>-} \
>-\
>-__gen_read(func, 8) \
>-__gen_read(func, 16) \
>-__gen_read(func, 32) \
>-__gen_read(func, 64)
>+static enum forcewake_domains
>+fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
>+	return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
>+}
>
>-__gen_reg_read_funcs(gen11_fwtable);
>-__gen_reg_read_funcs(fwtable);
>+__gen_fwtable_read(8)
>+__gen_fwtable_read(16)
>+__gen_fwtable_read(32)
>+__gen_fwtable_read(64)
>
>-#undef __gen_reg_read_funcs
>+#undef __gen_fwtable_read
> #undef GEN6_READ_FOOTER
> #undef GEN6_READ_HEADER
>
>@@ -2062,22 +2056,22 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
> 		ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
> 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
> 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> 		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
> 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
> 	} else if (GRAPHICS_VER(i915) >= 12) {
> 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
> 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
> 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
> 	} else if (GRAPHICS_VER(i915) == 11) {
> 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
> 		ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
> 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
>-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
>+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);

these together with patch 1 make the fwtable variant be the only one
used for reads.... so, should we pull these assignments out of if/else
chain? gen < 6 don't have forcewake so afaics we cover all the
platforms.

this can be done as a separate patch though.


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> 	} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
> 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
> 		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);
>-- 
>2.25.4
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index bfb2a6337f9d..10f124297e7c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -935,9 +935,6 @@  static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 	__fwd; \
 })
 
-#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
-	find_fw_domain(uncore, offset)
-
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const struct i915_range gen8_shadowed_regs[] = {
 	{ .start =  0x2030, .end =  0x2030 },
@@ -1570,33 +1567,30 @@  static inline void __force_wake_auto(struct intel_uncore *uncore,
 		___force_wake_auto(uncore, fw_domains);
 }
 
-#define __gen_read(func, x) \
+#define __gen_fwtable_read(x) \
 static u##x \
-func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
+fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
+{ \
 	enum forcewake_domains fw_engine; \
 	GEN6_READ_HEADER(x); \
-	fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
+	fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \
 	if (fw_engine) \
 		__force_wake_auto(uncore, fw_engine); \
 	val = __raw_uncore_read##x(uncore, reg); \
 	GEN6_READ_FOOTER; \
 }
 
-#define __gen_reg_read_funcs(func) \
-static enum forcewake_domains \
-func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
-	return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
-} \
-\
-__gen_read(func, 8) \
-__gen_read(func, 16) \
-__gen_read(func, 32) \
-__gen_read(func, 64)
+static enum forcewake_domains
+fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
+	return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));
+}
 
-__gen_reg_read_funcs(gen11_fwtable);
-__gen_reg_read_funcs(fwtable);
+__gen_fwtable_read(8)
+__gen_fwtable_read(16)
+__gen_fwtable_read(32)
+__gen_fwtable_read(64)
 
-#undef __gen_reg_read_funcs
+#undef __gen_fwtable_read
 #undef GEN6_READ_FOOTER
 #undef GEN6_READ_HEADER
 
@@ -2062,22 +2056,22 @@  static int uncore_forcewake_init(struct intel_uncore *uncore)
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (GRAPHICS_VER(i915) == 11) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (IS_GRAPHICS_VER(i915, 9, 10)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
 		ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs);