diff mbox series

[v12,05/35] dt-bindings: clock: tegra-car: Document new clock sub-nodes

Message ID 20210920181145.19543-6-digetx@gmail.com (mailing list archive)
State New, archived
Headers show
Series NVIDIA Tegra power management patches for 5.16 | expand

Commit Message

Dmitry Osipenko Sept. 20, 2021, 6:11 p.m. UTC
Document sub-nodes which describe Tegra SoC clocks that require a higher
voltage of the core power domain in order to operate properly on a higher
clock rates.  Each node contains a phandle to OPP table and power domain.

The root PLLs and system clocks don't have any specific device dedicated
to them, clock controller is in charge of managing power for them.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 .../bindings/clock/nvidia,tegra20-car.yaml    | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)

Comments

Rob Herring (Arm) Sept. 23, 2021, 9:09 p.m. UTC | #1
On Mon, 20 Sep 2021 21:11:15 +0300, Dmitry Osipenko wrote:
> Document sub-nodes which describe Tegra SoC clocks that require a higher
> voltage of the core power domain in order to operate properly on a higher
> clock rates.  Each node contains a phandle to OPP table and power domain.
> 
> The root PLLs and system clocks don't have any specific device dedicated
> to them, clock controller is in charge of managing power for them.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  .../bindings/clock/nvidia,tegra20-car.yaml    | 37 +++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>
Stephen Boyd Oct. 15, 2021, 12:16 a.m. UTC | #2
Quoting Dmitry Osipenko (2021-09-20 11:11:15)
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> index 459d2a525393..f832abb7f11a 100644
> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> @@ -42,6 +42,36 @@ properties:
>    "#reset-cells":
>      const: 1
>  
> +patternProperties:
> +  "^(sclk)|(pll-[cem])$":
> +    type: object
> +    properties:
> +      compatible:
> +        enum:
> +          - nvidia,tegra20-sclk
> +          - nvidia,tegra30-sclk
> +          - nvidia,tegra30-pllc
> +          - nvidia,tegra30-plle
> +          - nvidia,tegra30-pllm
> +
> +      operating-points-v2: true
> +
> +      clocks:
> +        items:
> +          - description: node's clock
> +
> +      power-domains:
> +        maxItems: 1
> +        description: phandle to the core SoC power domain

Is this done to associate the power domain with a particular clk? And an
OPP table with a particular clk?

> +
> +    required:
> +      - compatible
> +      - operating-points-v2
> +      - clocks
> +      - power-domains
> +
> +    additionalProperties: false
> +
>  required:
>    - compatible
>    - reg
Dmitry Osipenko Oct. 15, 2021, 12:43 a.m. UTC | #3
15.10.2021 03:16, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2021-09-20 11:11:15)
>> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> index 459d2a525393..f832abb7f11a 100644
>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>> @@ -42,6 +42,36 @@ properties:
>>    "#reset-cells":
>>      const: 1
>>  
>> +patternProperties:
>> +  "^(sclk)|(pll-[cem])$":
>> +    type: object
>> +    properties:
>> +      compatible:
>> +        enum:
>> +          - nvidia,tegra20-sclk
>> +          - nvidia,tegra30-sclk
>> +          - nvidia,tegra30-pllc
>> +          - nvidia,tegra30-plle
>> +          - nvidia,tegra30-pllm
>> +
>> +      operating-points-v2: true
>> +
>> +      clocks:
>> +        items:
>> +          - description: node's clock
>> +
>> +      power-domains:
>> +        maxItems: 1
>> +        description: phandle to the core SoC power domain
> 
> Is this done to associate the power domain with a particular clk? And an
> OPP table with a particular clk?

Yes
Stephen Boyd Oct. 15, 2021, 12:45 a.m. UTC | #4
Quoting Dmitry Osipenko (2021-10-14 17:43:49)
> 15.10.2021 03:16, Stephen Boyd пишет:
> > Quoting Dmitry Osipenko (2021-09-20 11:11:15)
> >> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> >> index 459d2a525393..f832abb7f11a 100644
> >> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> >> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
> >> @@ -42,6 +42,36 @@ properties:
> >>    "#reset-cells":
> >>      const: 1
> >>  
> >> +patternProperties:
> >> +  "^(sclk)|(pll-[cem])$":
> >> +    type: object
> >> +    properties:
> >> +      compatible:
> >> +        enum:
> >> +          - nvidia,tegra20-sclk
> >> +          - nvidia,tegra30-sclk
> >> +          - nvidia,tegra30-pllc
> >> +          - nvidia,tegra30-plle
> >> +          - nvidia,tegra30-pllm
> >> +
> >> +      operating-points-v2: true
> >> +
> >> +      clocks:
> >> +        items:
> >> +          - description: node's clock
> >> +
> >> +      power-domains:
> >> +        maxItems: 1
> >> +        description: phandle to the core SoC power domain
> > 
> > Is this done to associate the power domain with a particular clk? And an
> > OPP table with a particular clk?
> 
> Yes
> 

Ok. Can Ulf/Viresh review this patch series?
Dmitry Osipenko Oct. 15, 2021, 1:02 a.m. UTC | #5
15.10.2021 03:45, Stephen Boyd пишет:
> Quoting Dmitry Osipenko (2021-10-14 17:43:49)
>> 15.10.2021 03:16, Stephen Boyd пишет:
>>> Quoting Dmitry Osipenko (2021-09-20 11:11:15)
>>>> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>>>> index 459d2a525393..f832abb7f11a 100644
>>>> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>>>> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
>>>> @@ -42,6 +42,36 @@ properties:
>>>>    "#reset-cells":
>>>>      const: 1
>>>>  
>>>> +patternProperties:
>>>> +  "^(sclk)|(pll-[cem])$":
>>>> +    type: object
>>>> +    properties:
>>>> +      compatible:
>>>> +        enum:
>>>> +          - nvidia,tegra20-sclk
>>>> +          - nvidia,tegra30-sclk
>>>> +          - nvidia,tegra30-pllc
>>>> +          - nvidia,tegra30-plle
>>>> +          - nvidia,tegra30-pllm
>>>> +
>>>> +      operating-points-v2: true
>>>> +
>>>> +      clocks:
>>>> +        items:
>>>> +          - description: node's clock
>>>> +
>>>> +      power-domains:
>>>> +        maxItems: 1
>>>> +        description: phandle to the core SoC power domain
>>>
>>> Is this done to associate the power domain with a particular clk? And an
>>> OPP table with a particular clk?
>>
>> Yes
>>
> 
> Ok. Can Ulf/Viresh review this patch series?

They already did, please see v13 [1].

[1] https://lore.kernel.org/lkml/20210926224058.1252-1-digetx@gmail.com/
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
index 459d2a525393..f832abb7f11a 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
@@ -42,6 +42,36 @@  properties:
   "#reset-cells":
     const: 1
 
+patternProperties:
+  "^(sclk)|(pll-[cem])$":
+    type: object
+    properties:
+      compatible:
+        enum:
+          - nvidia,tegra20-sclk
+          - nvidia,tegra30-sclk
+          - nvidia,tegra30-pllc
+          - nvidia,tegra30-plle
+          - nvidia,tegra30-pllm
+
+      operating-points-v2: true
+
+      clocks:
+        items:
+          - description: node's clock
+
+      power-domains:
+        maxItems: 1
+        description: phandle to the core SoC power domain
+
+    required:
+      - compatible
+      - operating-points-v2
+      - clocks
+      - power-domains
+
+    additionalProperties: false
+
 required:
   - compatible
   - reg
@@ -59,6 +89,13 @@  examples:
         reg = <0x60006000 0x1000>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+
+        sclk {
+            compatible = "nvidia,tegra20-sclk";
+            operating-points-v2 = <&opp_table>;
+            clocks = <&tegra_car TEGRA20_CLK_SCLK>;
+            power-domains = <&domain>;
+        };
     };
 
     usb-controller@c5004000 {