From patchwork Fri Sep 24 23:23:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12517007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30340C433F5 for ; Fri, 24 Sep 2021 23:24:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB3DF61260 for ; Fri, 24 Sep 2021 23:24:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DB3DF61260 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 06D156EE95; Fri, 24 Sep 2021 23:24:00 +0000 (UTC) Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E3876E2A3 for ; Fri, 24 Sep 2021 23:23:58 +0000 (UTC) Received: by mail-pj1-x1035.google.com with SMTP id r7so7472531pjo.3 for ; Fri, 24 Sep 2021 16:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tZGh0IJWufh01powSTdVx5YAdtheJ5mkv5nCF0lb+5k=; b=Bdypi4AoRYyPQV/WrOBQVtgF+UF/fI2bXzxtvauSLQOCVb5r0rfFvfICzo4AoUNQxp mmCTqJk4sH469ZT8FEzHZE5VPXYygqhS2HTnQ0HkQQMt6rEQcQqsC46gRqemwGhWM7Y4 e8OF69jqXcNw3uI9AdlSAi5V7GO9lh6g/Un5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tZGh0IJWufh01powSTdVx5YAdtheJ5mkv5nCF0lb+5k=; b=toF1rl805RCpHH01sVnypl3OmW+2gEjmmzIaLYR5VJvenfzNeFDPeFFnTCZEDh12Hd etLdgmEofX2VPS9yI92tyCwnd3jXPWSz1uNyyQgXYAWTdzAYoPZL1A38y8MQkyTwTbCN sEn272paT/oY+Cime1s6HRmPiKj22ONyU/X9+W1KoNpk3w5Y5G7S4MLv/NYdlqJFMlR2 ACAbSBoJgupfIoguaz/fWaWOL1uTInzAc+jvhuQYT0iK328bwNveO/nZtLShOpJqKRA/ dejN+HFOkqXfNX2m/jTlVpGieq5C3TYU4ZHZxlxhL+/uDibOY5Mcj5HanaJbLqUWYI22 K4xQ== X-Gm-Message-State: AOAM530lsOiKq9zw0+Ij2uKYonOhBNGz52jzMNRBBZrzRw3bju9OLCof qXi1QfZgpoF+MjoK7FmUg0r2hIGkWuvQ5A== X-Google-Smtp-Source: ABdhPJyj7C/w++WE5M0qMOoytO2CFEADcDfViRtt1xg+ksq9CtCLBoM8O3bLexZsO3TOlq4YFbWnuQ== X-Received: by 2002:a17:902:7144:b0:13c:8d49:fc46 with SMTP id u4-20020a170902714400b0013c8d49fc46mr11073502plm.45.1632525837863; Fri, 24 Sep 2021 16:23:57 -0700 (PDT) Received: from localhost ([2620:15c:202:201:74de:c8b7:3a35:1063]) by smtp.gmail.com with UTF8SMTPSA id b12sm9792028pfp.5.2021.09.24.16.23.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Sep 2021 16:23:57 -0700 (PDT) From: Brian Norris To: =?utf-8?q?Heiko_St=C3=BCbner?= Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sandy Huang , linux-rockchip@lists.infradead.org, Thomas Hebb , Brian Norris , aleksandr.o.makarov@gmail.com, stable@vger.kernel.org Subject: [PATCH 1/2] drm/rockchip: dsi: hold pm-runtime across bind/unbind Date: Fri, 24 Sep 2021 16:23:45 -0700 Message-Id: <20210924162321.1.Ic2904d37f30013a7f3d8476203ad3733c186827e@changeid> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In commit 59eb7193bef2, we moved most HW configuration to bind(), but we didn't move the runtime PM management. Therefore, depending on initial boot state, runtime-PM workqueue delays, and other timing factors, we may disable our power domain in between the hardware configuration (bind()) and when we enable the display. This can cause us to lose hardware state and fail to configure our display. For example: dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO panel-innolux-p079zca ff960000.mipi.0: failed to write command 0 or: dw-mipi-dsi-rockchip ff968000.mipi: failed to write command FIFO panel-kingdisplay-kd097d04 ff960000.mipi.0: failed write init cmds: -110 We should match the runtime PM to the lifetime of the bind()/unbind() cycle. Tested on Acer Chrometab 10 (RK3399 Gru-Scarlet), with panel drivers built either as modules or built-in. Side notes: it seems one is more likely to see this problem when the panel driver is built into the kernel. I've also seen this problem bisect down to commits that simply changed Kconfig dependencies, because it changed the order in which driver init functions were compiled into the kernel, and therefore the ordering and timing of built-in device probe. Fixes: 59eb7193bef2 ("drm/rockchip: dsi: move all lane config except LCDC mux to bind()") Link: https://lore.kernel.org/linux-rockchip/9aedfb528600ecf871885f7293ca4207c84d16c1.camel@gmail.com/ Reported-by: Cc: Signed-off-by: Brian Norris Tested-by: Nícolas F. R. A. Prado --- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 22 +++++++------------ 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index a2262bee5aa4..4340a99edb97 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -773,10 +773,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) if (mux < 0) return; - pm_runtime_get_sync(dsi->dev); - if (dsi->slave) - pm_runtime_get_sync(dsi->slave->dev); - /* * For the RK3399, the clk of grf must be enabled before writing grf * register. And for RK3288 or other soc, this grf_clk must be NULL, @@ -795,20 +791,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) clk_disable_unprepare(dsi->grf_clk); } -static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) -{ - struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); - - if (dsi->slave) - pm_runtime_put(dsi->slave->dev); - pm_runtime_put(dsi->dev); -} - static const struct drm_encoder_helper_funcs dw_mipi_dsi_encoder_helper_funcs = { .atomic_check = dw_mipi_dsi_encoder_atomic_check, .enable = dw_mipi_dsi_encoder_enable, - .disable = dw_mipi_dsi_encoder_disable, }; static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, @@ -938,6 +924,10 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, put_device(second); } + pm_runtime_get_sync(dsi->dev); + if (dsi->slave) + pm_runtime_get_sync(dsi->slave->dev); + ret = clk_prepare_enable(dsi->pllref_clk); if (ret) { DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); @@ -989,6 +979,10 @@ static void dw_mipi_dsi_rockchip_unbind(struct device *dev, dw_mipi_dsi_unbind(dsi->dmd); clk_disable_unprepare(dsi->pllref_clk); + + pm_runtime_put(dsi->dev); + if (dsi->slave) + pm_runtime_put(dsi->slave->dev); } static const struct component_ops dw_mipi_dsi_rockchip_ops = {