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[2a02:8440:6441:43a4:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id g18sm12655132wmq.4.2021.12.17.07.09.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Dec 2021 07:09:25 -0800 (PST) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger Subject: [PATCH v7 5/8] drm/mediatek: dpi: Add dpintf support Date: Fri, 17 Dec 2021 16:08:51 +0100 Message-Id: <20211217150854.2081-6-granquet@baylibre.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211217150854.2081-1-granquet@baylibre.com> References: <20211217150854.2081-1-granquet@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Markus Schneider-Pargmann , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Markus Schneider-Pargmann dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 304 ++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 2 + 6 files changed, 299 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4554e2de14309..fbc43ea4049b9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL }; +enum TVDPLL_CLK { + TVDPLL_PLL = 0, + TVDPLL_D2 = 2, + TVDPLL_D4 = 4, + TVDPLL_D8 = 8, + TVDPLL_D16 = 16, +}; + struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; @@ -71,8 +79,10 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *dpi_ck_cg; struct clk *pixel_clk; struct clk *tvd_clk; + struct clk *pclk_src[5]; int irq; struct drm_display_mode mode; const struct mtk_dpi_conf *conf; @@ -125,6 +135,18 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; + bool is_dpintf; + bool csc_support; + bool swap_input_support; + // Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) + u32 dimension_mask; + // Mask used for HSIZE and VSIZE (no shift) + u32 hvsize_mask; + u32 channel_swap_shift; + u32 yuv422_en_bit; + u32 csc_enable_bit; + const struct mtk_dpi_yc_limit *limit; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -153,30 +175,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -210,13 +232,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; - pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | + mask = HSYNC_POL | VSYNC_POL; + pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |= CK_POL | DE_POL; + pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -231,13 +260,16 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -332,17 +364,20 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, break; } - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, + CH_SWAP_MASK << dpi->conf->channel_swap_shift); } static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); } static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -361,25 +396,54 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) +{ + u32 matrix_sel = 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <= 720) + matrix_sel = 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); - mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->csc_support) { + mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); + } + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); - mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->csc_support) { + mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); + } + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); - mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->csc_support) + mtk_dpi_config_csc_enable(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -412,6 +476,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_ck_cg); + clk_disable_unprepare(dpi->tvd_clk); } static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -421,12 +487,24 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0; + ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_pixel; + } + ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_refcount; } + ret = clk_prepare_enable(dpi->dpi_ck_cg); + if (ret) { + dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret); + goto err_ck_cg; + } + ret = clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -436,10 +514,11 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); - mtk_dpi_enable(dpi); return 0; err_pixel: + clk_disable_unprepare(dpi->dpi_ck_cg); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; @@ -449,7 +528,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 }; @@ -472,32 +550,42 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk); vm.pixelclock = pll_rate / factor; - if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) + if (dpi->conf->is_dpintf) { + if (factor == 1) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + else if (factor == 2) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[3]); + else if (factor == 4) + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[4]); + else + clk_set_parent(dpi->pixel_clk, dpi->pclk_src[2]); + } else if { ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || + (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } vm.pixelclock = clk_get_rate(dpi->pixel_clk); dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); - limit.c_bottom = 0x0010; - limit.c_top = 0x0FE0; - limit.y_bottom = 0x0010; - limit.y_top = 0x0FE0; - dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width = vm.hsync_len; - hsync.back_porch = vm.hback_porch; - hsync.front_porch = vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width = vm.hsync_len / 4; + hsync.back_porch = vm.hback_porch / 4; + hsync.front_porch = vm.hfront_porch / 4; + } else { + hsync.sync_width = vm.hsync_len; + hsync.back_porch = vm.hback_porch; + hsync.front_porch = vm.hfront_porch; + } hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch; @@ -536,16 +624,23 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); + mtk_dpi_enable(dpi); + return 0; } @@ -588,7 +683,6 @@ static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, u32 *input_fmts; *num_input_fmts = 0; - input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); if (!input_fmts) @@ -614,15 +708,18 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, if (dpi->conf->num_output_fmts) out_bus_format = dpi->conf->output_fmts[0]; - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + dev_info(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); dpi->output_fmt = out_bus_format; dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; return 0; } @@ -667,7 +764,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi = bridge_to_dpi(bridge); - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; return MODE_OK; @@ -781,6 +878,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -790,12 +897,41 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, }; +static const u32 mt8195_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { + .c_bottom = 0x0010, + .c_top = 0x0FE0, + .y_bottom = 0x0010, + .y_top = 0x0FE0, +}; + +static const struct mtk_dpi_yc_limit mtk_dpintf_limit = { + .c_bottom = 0x0000, + .c_top = 0xFFF, + .y_bottom = 0x0000, + .y_top = 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, + .csc_support = true, + .swap_input_support = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt2701_conf = { @@ -805,6 +941,15 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, + .csc_support = true, + .swap_input_support = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8183_conf = { @@ -813,6 +958,15 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol = true, + .csc_support = true, + .swap_input_support = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8192_conf = { @@ -821,6 +975,29 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, + .csc_support = true, + .swap_input_support = true, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, + .limit = &mtk_dpi_limit, +}; + +static const struct mtk_dpi_conf mt8195_dpintf_conf = { + .cal_factor = mt8195_dpintf_calculate_factor, + .output_fmts = mt8195_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf = true, + .csc_support = true, + .dimension_mask = DPINTF_HPW_MASK, + .hvsize_mask = DPINTF_HSIZE_MASK, + .channel_swap_shift = DPINTF_CH_SWAP, + .yuv422_en_bit = DPINTF_YUV422_EN, + .csc_enable_bit = DPINTF_CSC_ENABLE, + .limit = &mtk_dpintf_limit, }; static int mtk_dpi_probe(struct platform_device *pdev) @@ -870,7 +1047,18 @@ static int mtk_dpi_probe(struct platform_device *pdev) if (IS_ERR(dpi->engine_clk)) { ret = PTR_ERR(dpi->engine_clk); if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to get engine clock: %d\n", ret); + dev_err(dev, "Failed to get engine clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg = devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret = PTR_ERR(dpi->dpi_ck_cg); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", + ret); return ret; } @@ -893,6 +1081,11 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } + dpi->pclk_src[1] = devm_clk_get(dev, "TVDPLL_D2"); + dpi->pclk_src[2] = devm_clk_get(dev, "TVDPLL_D4"); + dpi->pclk_src[3] = devm_clk_get(dev, "TVDPLL_D8"); + dpi->pclk_src[4] = devm_clk_get(dev, "TVDPLL_D16"); + dpi->irq = platform_get_irq(pdev, 0); if (dpi->irq <= 0) return -EINVAL; @@ -945,6 +1138,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, + { .compatible = "mediatek,mt8195-dpintf", + .data = &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe16627..91b32dfffced2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,29 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL BIT(0) +#define INT_MATRIX_SEL_MASK (0x1F << 0) +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 99cbf44463e40..0a9fc9d6d3cb3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -317,6 +317,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_UFOE] = "ufoe", [MTK_DSI] = "dsi", [MTK_DPI] = "dpi", + [MTK_DP_INTF] = "dp-intf", [MTK_DISP_PWM] = "pwm", [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", @@ -339,6 +340,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, @@ -476,6 +479,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || + type == MTK_DP_INTF || type == MTK_DSI || type == MTK_DISP_OVL || type == MTK_DISP_OVL_2L || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..ee9d853cfa1c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DP_INTF, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index aec39724ebeb6..1ff4e31c86345 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -459,6 +459,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8183-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8195-dpintf", + .data = (void *)MTK_DP_INTF }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", @@ -569,7 +571,8 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_RDMA || comp_type == MTK_DSI || - comp_type == MTK_DPI) { + comp_type == MTK_DPI || + comp_type == MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4bba275e235ac..56ed2fa5f59e8 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -19,6 +19,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DITHER, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2,