diff mbox series

[v5,2/6] drm/vc4: hdmi: Move clock calculation into its own function

Message ID 20220127141021.302482-3-maxime@cerno.tech (mailing list archive)
State New, archived
Headers show
Series drm/vc4: hdmi: Yet Another Approach to HDMI YUV output | expand

Commit Message

Maxime Ripard Jan. 27, 2022, 2:10 p.m. UTC
The code to compute our clock rate for a given setup will be called in
multiple places in the next patches, so let's create a separate function
for it.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/gpu/drm/vc4/vc4_hdmi.c | 49 +++++++++++++++++++++++-----------
 1 file changed, 34 insertions(+), 15 deletions(-)

Comments

Ville Syrjala Feb. 3, 2022, 7:59 p.m. UTC | #1
On Thu, Jan 27, 2022 at 03:10:17PM +0100, Maxime Ripard wrote:
> The code to compute our clock rate for a given setup will be called in
> multiple places in the next patches, so let's create a separate function
> for it.
> 
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
>  drivers/gpu/drm/vc4/vc4_hdmi.c | 49 +++++++++++++++++++++++-----------
>  1 file changed, 34 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index 105911644b02..a1fa37ad350d 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -1274,6 +1274,35 @@ vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
>  	return MODE_OK;
>  }
>  
> +static unsigned long long
> +vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
> +				    unsigned int bpc)
> +{
> +	unsigned long long clock = mode->clock * 1000;
> +
> +	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> +		clock = clock * 2;
> +
> +	return clock * bpc / 8;

div_u64()/etc.?

> +}
> +
> +static int
> +vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
> +			       struct vc4_hdmi_connector_state *vc4_state,
> +			       const struct drm_display_mode *mode,
> +			       unsigned int bpc)
> +{
> +	unsigned long long clock;
> +
> +	clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
> +	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
> +		return -EINVAL;
> +
> +	vc4_state->pixel_rate = clock;

This thing seems a bit confused between pixels vs. TMDS characters.
Either that or some/all of the pixel_clock/rate things are just
misnamed?

> +
> +	return 0;
> +}
> +
>  #define WIFI_2_4GHz_CH1_MIN_FREQ	2400000000ULL
>  #define WIFI_2_4GHz_CH1_MAX_FREQ	2422000000ULL
>  
> @@ -1286,6 +1315,7 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
>  	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
>  	unsigned long long pixel_rate = mode->clock * 1000;
>  	unsigned long long tmds_rate;
> +	int ret;
>  
>  	if (vc4_hdmi->variant->unsupported_odd_h_timings &&
>  	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
> @@ -1306,21 +1336,10 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
>  		pixel_rate = mode->clock * 1000;
>  	}
>  
> -	if (conn_state->max_bpc == 12) {
> -		pixel_rate = pixel_rate * 150;
> -		do_div(pixel_rate, 100);
> -	} else if (conn_state->max_bpc == 10) {
> -		pixel_rate = pixel_rate * 125;
> -		do_div(pixel_rate, 100);
> -	}
> -
> -	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> -		pixel_rate = pixel_rate * 2;
> -
> -	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, pixel_rate) != MODE_OK)
> -		return -EINVAL;
> -
> -	vc4_state->pixel_rate = pixel_rate;
> +	ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, mode,
> +					     conn_state->max_bpc);
> +	if (ret)
> +		return ret;
>  
>  	return 0;
>  }
> -- 
> 2.34.1
Maxime Ripard Feb. 10, 2022, 9 a.m. UTC | #2
Hi Ville,

Thanks for your review

On Thu, Feb 03, 2022 at 09:59:15PM +0200, Ville Syrjälä wrote:
> > +static int
> > +vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
> > +			       struct vc4_hdmi_connector_state *vc4_state,
> > +			       const struct drm_display_mode *mode,
> > +			       unsigned int bpc)
> > +{
> > +	unsigned long long clock;
> > +
> > +	clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
> > +	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
> > +		return -EINVAL;
> > +
> > +	vc4_state->pixel_rate = clock;
> 
> This thing seems a bit confused between pixels vs. TMDS characters.
> Either that or some/all of the pixel_clock/rate things are just
> misnamed?

Yeah, this is the TMDS characters rate, I'll rename it.

Maxime
diff mbox series

Patch

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 105911644b02..a1fa37ad350d 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1274,6 +1274,35 @@  vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
 	return MODE_OK;
 }
 
+static unsigned long long
+vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
+				    unsigned int bpc)
+{
+	unsigned long long clock = mode->clock * 1000;
+
+	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+		clock = clock * 2;
+
+	return clock * bpc / 8;
+}
+
+static int
+vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
+			       struct vc4_hdmi_connector_state *vc4_state,
+			       const struct drm_display_mode *mode,
+			       unsigned int bpc)
+{
+	unsigned long long clock;
+
+	clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
+	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
+		return -EINVAL;
+
+	vc4_state->pixel_rate = clock;
+
+	return 0;
+}
+
 #define WIFI_2_4GHz_CH1_MIN_FREQ	2400000000ULL
 #define WIFI_2_4GHz_CH1_MAX_FREQ	2422000000ULL
 
@@ -1286,6 +1315,7 @@  static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 	struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 	unsigned long long pixel_rate = mode->clock * 1000;
 	unsigned long long tmds_rate;
+	int ret;
 
 	if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 	    ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
@@ -1306,21 +1336,10 @@  static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 		pixel_rate = mode->clock * 1000;
 	}
 
-	if (conn_state->max_bpc == 12) {
-		pixel_rate = pixel_rate * 150;
-		do_div(pixel_rate, 100);
-	} else if (conn_state->max_bpc == 10) {
-		pixel_rate = pixel_rate * 125;
-		do_div(pixel_rate, 100);
-	}
-
-	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-		pixel_rate = pixel_rate * 2;
-
-	if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, pixel_rate) != MODE_OK)
-		return -EINVAL;
-
-	vc4_state->pixel_rate = pixel_rate;
+	ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, mode,
+					     conn_state->max_bpc);
+	if (ret)
+		return ret;
 
 	return 0;
 }