| Message ID | 20220207203642.1875208-1-John.C.Harrison@Intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/i915/dg2: Define GuC firmware version for DG2 | expand |
Hmm, this is actually v1 not v3! Had something stale when posting. John. On 2/7/2022 12:36, John.C.Harrison@Intel.com wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > First release of GuC for DG2. > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > CC: Tomasz Mistat <tomasz.mistat@intel.com> > CC: Ramalingam C <ramalingam.c@intel.com> > CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index ba4f0970749b..efe0a6dcf9f7 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -50,6 +50,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, > * firmware as TGL. > */ > #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ > + fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ > fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ > fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ > fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \
On Mon, Feb 07, 2022 at 12:36:42PM -0800, John.C.Harrison@Intel.com wrote: >From: John Harrison <John.C.Harrison@Intel.com> > >First release of GuC for DG2. > >Signed-off-by: John Harrison <John.C.Harrison@Intel.com> >CC: Tomasz Mistat <tomasz.mistat@intel.com> >CC: Ramalingam C <ramalingam.c@intel.com> >CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi >--- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 + > 1 file changed, 1 insertion(+) > >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >index ba4f0970749b..efe0a6dcf9f7 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >@@ -50,6 +50,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, > * firmware as TGL. > */ > #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ >+ fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ > fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ > fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ > fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \ >-- >2.25.1 >
+Daniele, +Rodrigo On Tue, Feb 08, 2022 at 11:14:57PM -0800, Lucas De Marchi wrote: >On Mon, Feb 07, 2022 at 12:36:42PM -0800, John.C.Harrison@Intel.com wrote: >>From: John Harrison <John.C.Harrison@Intel.com> >> >>First release of GuC for DG2. >> >>Signed-off-by: John Harrison <John.C.Harrison@Intel.com> >>CC: Tomasz Mistat <tomasz.mistat@intel.com> >>CC: Ramalingam C <ramalingam.c@intel.com> >>CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > >Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> I rebased topic/core-for-CI on v5.17-rc4 that is where drm/drm-next is based at and applied this patch there. Even after the rebase there was a small conflict that I fixed up. As talked with Daniele, we decided to merge this in the topic branch so we can enable CI first and don't risk needing 2 versions sent to linux-firmware if something doesn't work. However I think we can't leave this patch there for a long time, otherwise it will cause conflicts for things merging in drm-intel-gt-next soon. Daniele, while merging this I forgot to add the r-b you gave in the other email thread, sorry. We can add it when this goes to the normal non-topic branch. thanks Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index ba4f0970749b..efe0a6dcf9f7 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -50,6 +50,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * firmware as TGL. */ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ + fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \