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Wed, 9 Feb 2022 08:51:27 +0000 From: Michael Riesch To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v5 2/5] arm64: dts: rockchip: add gpu node to rk356x Date: Wed, 9 Feb 2022 09:51:07 +0100 Message-Id: <20220209085110.3588035-3-michael.riesch@wolfvision.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220209085110.3588035-1-michael.riesch@wolfvision.net> References: <20220209085110.3588035-1-michael.riesch@wolfvision.net> X-ClientProxiedBy: ZR0P278CA0072.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:21::23) To HE1PR0802MB2426.eurprd08.prod.outlook.com (2603:10a6:3:e1::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c048c59b-621d-492a-1e11-08d9eba95b91 X-MS-TrafficTypeDiagnostic: VI1PR08MB2927:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:983; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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It has one shader core and two execution engines. Quoting the datasheet: Mali-G52 1-Core-2EE * Support 1600Mpix/s fill rate when 800MHz clock frequency * Support 38.4GLOPs when 800MHz clock frequency Signed-off-by: Ezequiel Garcia Signed-off-by: Alex Bee Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index ff1689283996..47484305b7a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -144,6 +144,40 @@ scmi_clk: protocol@14 { }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = , @@ -444,6 +478,21 @@ power-domain@RK3568_PD_RKVENC { }; }; + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "core", "bus"; + #cooling-cells = <2>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>;