| Message ID | 20220211054903.24671-1-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dg2: Don't try to process TBT interrupts | expand |
On Fri, Feb 11, 2022 at 11:19:03AM +0530, Ramalingam C wrote: > From: Matt Roper <matthew.d.roper@intel.com> > > DG2 is the first platform, that supports TC but not TBT. > interrupt code is updated to avoid trying to process > TBT-specific bits and registers. Is that a real concern? > > Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++---- > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 5b6fd792a8d7..b9294ff5a1e6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1433,6 +1433,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > +#define HAS_TC_WITHOUT_TBT(dev_priv) (INTEL_INFO(dev_priv)->display.has_tc_without_tbt) > #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index fdd568ba4a16..72b9888b2acf 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2245,7 +2245,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) > { > u32 pin_mask = 0, long_mask = 0; > u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; > - u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; > + u32 trigger_tbt = HAS_TC_WITHOUT_TBT(dev_priv) ? 0 : > + iir & GEN11_DE_TBT_HOTPLUG_MASK; > > if (trigger_tc) { > u32 dig_hotplug_reg; > @@ -3468,7 +3469,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) > intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); Just above here is where the problem happens because it will unmask all the TBT irqs. I'm thinking we might want to split hpd_gen11[] into tc vs. tbt variants and introduce i915->hotplug.hpd_tbt[]. > > gen11_tc_hpd_detection_setup(dev_priv); > - gen11_tbt_hpd_detection_setup(dev_priv); > + if (!HAS_TC_WITHOUT_TBT(dev_priv)) > + gen11_tbt_hpd_detection_setup(dev_priv); Does the GEN11_TBT_HOTPLUG_CTL register still exist though? If yes, then we probably want to keep initializing it, just making sure to turn off the relevant bits. > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > icp_hpd_irq_setup(dev_priv); > @@ -3828,8 +3830,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > if (DISPLAY_VER(dev_priv) >= 11) { > u32 de_hpd_masked = 0; > - u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | > - GEN11_DE_TBT_HOTPLUG_MASK; > + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK; > + > + if (!HAS_TC_WITHOUT_TBT(dev_priv)) > + de_hpd_enables |= GEN11_DE_TBT_HOTPLUG_MASK; > > GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, > de_hpd_enables); This code seems fine as is. It just sets all the enable bits but leaves everything masked. Exactly as everything else is handled (minus the odd SDEIER expection). > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 467252f885c2..1ad5593e925f 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -1046,6 +1046,7 @@ static const struct intel_device_info dg2_info = { > .graphics.rel = 55, > .media.rel = 55, > PLATFORM(INTEL_DG2), > + .display.has_tc_without_tbt = 1, > .has_guc_deprivilege = 1, > .has_64k_pages = 1, > .platform_engine_mask = > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 27dcfe6f2429..4d8cfd41aa31 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -171,6 +171,7 @@ enum intel_ppgtt_type { > func(has_overlay); \ > func(has_psr); \ > func(has_psr_hw_tracking); \ > + func(has_tc_without_tbt); \ > func(overlay_needs_physical); \ > func(supports_tv); > > -- > 2.20.1
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5b6fd792a8d7..b9294ff5a1e6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1433,6 +1433,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) +#define HAS_TC_WITHOUT_TBT(dev_priv) (INTEL_INFO(dev_priv)->display.has_tc_without_tbt) #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fdd568ba4a16..72b9888b2acf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2245,7 +2245,8 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) { u32 pin_mask = 0, long_mask = 0; u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; - u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; + u32 trigger_tbt = HAS_TC_WITHOUT_TBT(dev_priv) ? 0 : + iir & GEN11_DE_TBT_HOTPLUG_MASK; if (trigger_tc) { u32 dig_hotplug_reg; @@ -3468,7 +3469,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); gen11_tc_hpd_detection_setup(dev_priv); - gen11_tbt_hpd_detection_setup(dev_priv); + if (!HAS_TC_WITHOUT_TBT(dev_priv)) + gen11_tbt_hpd_detection_setup(dev_priv); if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) icp_hpd_irq_setup(dev_priv); @@ -3828,8 +3830,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 11) { u32 de_hpd_masked = 0; - u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | - GEN11_DE_TBT_HOTPLUG_MASK; + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK; + + if (!HAS_TC_WITHOUT_TBT(dev_priv)) + de_hpd_enables |= GEN11_DE_TBT_HOTPLUG_MASK; GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 467252f885c2..1ad5593e925f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1046,6 +1046,7 @@ static const struct intel_device_info dg2_info = { .graphics.rel = 55, .media.rel = 55, PLATFORM(INTEL_DG2), + .display.has_tc_without_tbt = 1, .has_guc_deprivilege = 1, .has_64k_pages = 1, .platform_engine_mask = diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 27dcfe6f2429..4d8cfd41aa31 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -171,6 +171,7 @@ enum intel_ppgtt_type { func(has_overlay); \ func(has_psr); \ func(has_psr_hw_tracking); \ + func(has_tc_without_tbt); \ func(overlay_needs_physical); \ func(supports_tv);