diff mbox series

drm/i915/perf: Skip the i915_perf_init for dg2

Message ID 20220215053115.6023-1-ramalingam.c@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/perf: Skip the i915_perf_init for dg2 | expand

Commit Message

Ramalingam C Feb. 15, 2022, 5:31 a.m. UTC
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Matthew Auld Feb. 15, 2022, 1:03 p.m. UTC | #1
On 15/02/2022 05:31, Ramalingam C wrote:
> i915_perf is not enabled for dg2 yet, hence skip the feature
> initialization.
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_perf.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 36f1325baa7d..5ac9604d07b3 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4373,6 +4373,10 @@ void i915_perf_init(struct drm_i915_private *i915)
>   
>   	/* XXX const struct i915_perf_ops! */
>   
> +	/* i915_perf is not enabled for DG2 yet */
> +	if (IS_DG2(i915))
> +		return;
> +
>   	perf->oa_formats = oa_formats;
>   	if (IS_HASWELL(i915)) {
>   		perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
Umesh Nerlige Ramappa Feb. 17, 2022, 7:13 p.m. UTC | #2
On Tue, Feb 15, 2022 at 11:01:15AM +0530, Ramalingam C wrote:
>i915_perf is not enabled for dg2 yet, hence skip the feature
>initialization.
>
>Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>---
> drivers/gpu/drm/i915/i915_perf.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index 36f1325baa7d..5ac9604d07b3 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -4373,6 +4373,10 @@ void i915_perf_init(struct drm_i915_private *i915)
>
> 	/* XXX const struct i915_perf_ops! */
>
>+	/* i915_perf is not enabled for DG2 yet */
>+	if (IS_DG2(i915))
>+		return;
>+

lgtm

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Thanks,
Umesh
> 	perf->oa_formats = oa_formats;
> 	if (IS_HASWELL(i915)) {
> 		perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
>-- 
>2.20.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 36f1325baa7d..5ac9604d07b3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4373,6 +4373,10 @@  void i915_perf_init(struct drm_i915_private *i915)
 
 	/* XXX const struct i915_perf_ops! */
 
+	/* i915_perf is not enabled for DG2 yet */
+	if (IS_DG2(i915))
+		return;
+
 	perf->oa_formats = oa_formats;
 	if (IS_HASWELL(i915)) {
 		perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;