diff mbox series

[v6,13/23] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always

Message ID 20220217082954.2967889-14-s.hauer@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series drm/rockchip: RK356x VOP2 support | expand

Commit Message

Sascha Hauer Feb. 17, 2022, 8:29 a.m. UTC 
From: Douglas Anderson <dianders@chromium.org>

Jitter was improved by lowering the MPLL bandwidth to account for high
frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
lowered only enough to get us a comfortable margin.  We believe that
lowering the bandwidth like this is safe given sufficient testing.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---

Notes:
    Changes since v3:
    - new patch

 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
 1 file changed, 2 insertions(+), 14 deletions(-)

Comments

Dmitry Osipenko Feb. 17, 2022, 2 p.m. UTC | #1 
17.02.2022 11:29, Sascha Hauer пишет:
> From: Douglas Anderson <dianders@chromium.org>
> 
> Jitter was improved by lowering the MPLL bandwidth to account for high
> frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
> lowered only enough to get us a comfortable margin.  We believe that
> lowering the bandwidth like this is safe given sufficient testing.

There are no device-trees that use "rockchip,rk3288-cru", AFAICS..

Was this change tested on a non-RK3288 devices?
Sascha Hauer Feb. 17, 2022, 3:12 p.m. UTC | #2 
On Thu, Feb 17, 2022 at 05:00:37PM +0300, Dmitry Osipenko wrote:
> 17.02.2022 11:29, Sascha Hauer пишет:
> > From: Douglas Anderson <dianders@chromium.org>
> > 
> > Jitter was improved by lowering the MPLL bandwidth to account for high
> > frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
> > lowered only enough to get us a comfortable margin.  We believe that
> > lowering the bandwidth like this is safe given sufficient testing.
> 
> There are no device-trees that use "rockchip,rk3288-cru", AFAICS..

What do you mean? In my tree I have:

arch/arm/boot/dts/rk3288.dtsi:863:              compatible = "rockchip,rk3288-cru";
drivers/clk/rockchip/clk-rk3288.c:985:CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);

> 
> Was this change tested on a non-RK3288 devices?

Yes, on a rk3568 ;)

The patch has been posted back in 2015 and was added to the Rockchip
downstream kernel in 2016. I don't know how thoroughly Rockchip tests
their kernels, but I assume the patch wouldn't be there if it caused
any problems.

Sascha
Dmitry Osipenko Feb. 17, 2022, 5 p.m. UTC | #3 
17.02.2022 18:12, Sascha Hauer пишет:
> On Thu, Feb 17, 2022 at 05:00:37PM +0300, Dmitry Osipenko wrote:
>> 17.02.2022 11:29, Sascha Hauer пишет:
>>> From: Douglas Anderson <dianders@chromium.org>
>>>
>>> Jitter was improved by lowering the MPLL bandwidth to account for high
>>> frequency noise in the rk3288 PLL.  In each case MPLL bandwidth was
>>> lowered only enough to get us a comfortable margin.  We believe that
>>> lowering the bandwidth like this is safe given sufficient testing.
>>
>> There are no device-trees that use "rockchip,rk3288-cru", AFAICS..
> 
> What do you mean? In my tree I have:
> 
> arch/arm/boot/dts/rk3288.dtsi:863:              compatible = "rockchip,rk3288-cru";
> drivers/clk/rockchip/clk-rk3288.c:985:CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);

Oh, it is ARM32, I was looking at ARM64 only. My bad.

>> Was this change tested on a non-RK3288 devices?
> 
> Yes, on a rk3568 ;)
> 
> The patch has been posted back in 2015 and was added to the Rockchip
> downstream kernel in 2016. I don't know how thoroughly Rockchip tests
> their kernels, but I assume the patch wouldn't be there if it caused
> any problems.

Thank you for the clarification.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index b48f137334ad6..4f2aff4b512d8 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -181,20 +181,8 @@  static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
 	/*      pixelclk    bpp8    bpp10   bpp12 */
 	{
-		40000000,  { 0x0018, 0x0018, 0x0018 },
-	}, {
-		65000000,  { 0x0028, 0x0028, 0x0028 },
-	}, {
-		66000000,  { 0x0038, 0x0038, 0x0038 },
-	}, {
-		74250000,  { 0x0028, 0x0038, 0x0038 },
-	}, {
-		83500000,  { 0x0028, 0x0038, 0x0038 },
-	}, {
-		146250000, { 0x0038, 0x0038, 0x0038 },
-	}, {
-		148500000, { 0x0000, 0x0038, 0x0038 },
-	}, {
+		600000000, { 0x0000, 0x0000, 0x0000 },
+	},  {
 		~0UL,      { 0x0000, 0x0000, 0x0000},
 	}
 };