| Message ID | 20220217202644.122937-2-michael.cheng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Move #define wbvind_on_all_cpus | expand |
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 66597e411764..722e3931d68a 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -40,8 +40,6 @@ #define MEMCPY_BOUNCE_SIZE 128 #if defined(CONFIG_X86) -#include <asm/smp.h> - /* * clflushopt is an unordered instruction which needs fencing with mfence or * sfence to avoid ordering issues. For drm_clflush_page this fencing happens diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index 22deb216b59c..24fcf6be1419 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -34,6 +34,12 @@ #define _DRM_CACHE_H_ #include <linux/scatterlist.h> +#include <asm/smp.h> + +#if !defined(CONFIG_x86) +#define wbinvd_on_all_cpus() \ + pr_warn("Missing cache flush in %s\n", __func__) +#endif struct iosys_map;
Add logic for wbvind_on_all_cpus for non-x86 platforms. v2(Michael Cheng): Change logic to if platform is not x86, then we add pr_warn for calling wbvind_on_all_cpus. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/drm_cache.c | 2 -- include/drm/drm_cache.h | 6 ++++++ 2 files changed, 6 insertions(+), 2 deletions(-)