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[6/7] drm/bridge: dw-mipi-dsi: Prefer DSI bus clock settings from bridge_state

Message ID 20220219002844.362157-7-marex@denx.de (mailing list archive)
State New, archived
Headers show
Series drm/bridge: Add support for selecting DSI host HS clock from DSI bridge | expand

Commit Message

Marek Vasut Feb. 19, 2022, 12:28 a.m. UTC 
The bridge_state now contains clock frequency required by the next bridge.
This information is optional, since very few drivers pass this information
now. In case the required clock frequency is part of bridge state, use it
for the DSI bus clock frequency, otherwise fall back to the old guesswork.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 0132e576339dd..e3fea94db9bfa 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -258,13 +258,17 @@  dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
 
 	pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
 
-	/* Compute requested pll out */
-	bpp = mipi_dsi_pixel_format_to_bpp(format);
-	pll_out_khz = mode->clock * bpp / lanes;
+	pll_out_khz = bridge_state->output_bus_cfg.clock;
 
-	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
-	if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
-		pll_out_khz = (pll_out_khz * 12) / 10;
+	if (pll_out_khz == 0) {
+		/* Guess requested pll out */
+		bpp = mipi_dsi_pixel_format_to_bpp(format);
+		pll_out_khz = mode->clock * bpp / lanes;
+
+		/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
+		if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+			pll_out_khz = (pll_out_khz * 12) / 10;
+	}
 
 	if (pll_out_khz > dsi->lane_max_kbps) {
 		pll_out_khz = dsi->lane_max_kbps;