| Message ID | 20220223114011.219044-1-marijn.suijten@somainline.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/msm/dpu: Bind pingpong block to intf on active ctls in cmd encoder | expand |
On Wed, 23 Feb 2022 at 14:40, Marijn Suijten <marijn.suijten@somainline.org> wrote: > > As per the specification of DPU_CTL_ACTIVE_CFG the configuration of > active blocks should be proactively specified, and the pingpong block is > no different. > > The downstream display driver [1] confirms this by also calling > bind_pingpong_blk on CTL_ACTIVE_CFG. Note that this else-if is always > entered, as setup_intf_cfg - unlike this mainline dpu driver that > combines both behind the same function pointer - is left NULL in favour > of using setup_intf_cfg_v1 when CTL_ACTIVE_CFG is set. > > This solves continuous timeouts on at least the Qualcomm sm6125 SoC: > > [drm:dpu_encoder_frame_done_timeout:2091] [dpu error]enc31 frame done timeout > [drm:_dpu_encoder_phys_cmd_handle_ppdone_timeout.isra.0] *ERROR* id:31 pp:0 kickoff timeout 0 cnt 1 koff_cnt 1 > [drm:dpu_encoder_phys_cmd_prepare_for_kickoff] *ERROR* failed wait_for_idle: id:31 ret:-110 pp:0 > > In the same way this pingpong block should also be unbound followed by > an interface flush when the encoder is disabled, according to the > downstream display driver [2]. > > [1]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder_phys_cmd.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n167 > [2]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n2986 > > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> As we are quite late in the development cycle, I'd delay this into the next release, if you don't mind. > --- > > Changes since v1: > - Always unbind the pingpong block in dpu_encoder_phys_cmd_disable, > instead of only if this encoder is the master. > > v1: https://lore.kernel.org/lkml/20211222105513.44860-1-marijn.suijten@somainline.org/ > > .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 8e433af7aea4..1be01cbd960e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -71,6 +71,13 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > intf_cfg.stream_sel = cmd_enc->stream_sel; > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > + > + /* setup which pp blk will connect to this intf */ > + if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) > + phys_enc->hw_intf->ops.bind_pingpong_blk( > + phys_enc->hw_intf, > + true, > + phys_enc->hw_pp->idx); > } > > static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) > @@ -507,6 +514,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) > { > struct dpu_encoder_phys_cmd *cmd_enc = > to_dpu_encoder_phys_cmd(phys_enc); > + struct dpu_hw_ctl *ctl; > > if (!phys_enc->hw_pp) { > DPU_ERROR("invalid encoder\n"); > @@ -523,6 +531,17 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) > > if (phys_enc->hw_pp->ops.enable_tearcheck) > phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); > + > + if (phys_enc->hw_intf->ops.bind_pingpong_blk) { > + phys_enc->hw_intf->ops.bind_pingpong_blk( > + phys_enc->hw_intf, > + false, > + phys_enc->hw_pp->idx); > + > + ctl = phys_enc->hw_ctl; > + ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx); > + } > + > phys_enc->enable_state = DPU_ENC_DISABLED; > } > > > base-commit: 3c30cf91b5ecc7272b3d2942ae0505dd8320b81c > -- > 2.35.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 8e433af7aea4..1be01cbd960e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -71,6 +71,13 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( intf_cfg.stream_sel = cmd_enc->stream_sel; intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); ctl->ops.setup_intf_cfg(ctl, &intf_cfg); + + /* setup which pp blk will connect to this intf */ + if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) + phys_enc->hw_intf->ops.bind_pingpong_blk( + phys_enc->hw_intf, + true, + phys_enc->hw_pp->idx); } static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) @@ -507,6 +514,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); + struct dpu_hw_ctl *ctl; if (!phys_enc->hw_pp) { DPU_ERROR("invalid encoder\n"); @@ -523,6 +531,17 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) if (phys_enc->hw_pp->ops.enable_tearcheck) phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); + + if (phys_enc->hw_intf->ops.bind_pingpong_blk) { + phys_enc->hw_intf->ops.bind_pingpong_blk( + phys_enc->hw_intf, + false, + phys_enc->hw_pp->idx); + + ctl = phys_enc->hw_ctl; + ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx); + } + phys_enc->enable_state = DPU_ENC_DISABLED; }
As per the specification of DPU_CTL_ACTIVE_CFG the configuration of active blocks should be proactively specified, and the pingpong block is no different. The downstream display driver [1] confirms this by also calling bind_pingpong_blk on CTL_ACTIVE_CFG. Note that this else-if is always entered, as setup_intf_cfg - unlike this mainline dpu driver that combines both behind the same function pointer - is left NULL in favour of using setup_intf_cfg_v1 when CTL_ACTIVE_CFG is set. This solves continuous timeouts on at least the Qualcomm sm6125 SoC: [drm:dpu_encoder_frame_done_timeout:2091] [dpu error]enc31 frame done timeout [drm:_dpu_encoder_phys_cmd_handle_ppdone_timeout.isra.0] *ERROR* id:31 pp:0 kickoff timeout 0 cnt 1 koff_cnt 1 [drm:dpu_encoder_phys_cmd_prepare_for_kickoff] *ERROR* failed wait_for_idle: id:31 ret:-110 pp:0 In the same way this pingpong block should also be unbound followed by an interface flush when the encoder is disabled, according to the downstream display driver [2]. [1]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder_phys_cmd.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n167 [2]: https://source.codeaurora.org/quic/la/platform/vendor/opensource/display-drivers/tree/msm/sde/sde_encoder.c?h=LA.UM.9.16.r1-08500-MANNAR.0#n2986 Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- Changes since v1: - Always unbind the pingpong block in dpu_encoder_phys_cmd_disable, instead of only if this encoder is the master. v1: https://lore.kernel.org/lkml/20211222105513.44860-1-marijn.suijten@somainline.org/ .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) base-commit: 3c30cf91b5ecc7272b3d2942ae0505dd8320b81c