| Message ID | 20220303223435.2793124-2-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/xehp: Support platforms with CCS engines but no RCS | expand |
On 3/3/2022 14:34, Matt Roper wrote: > From: Stuart Summers <stuart.summers@intel.com> > > If RCS is not enumerated, GuC will return invalid parameters. > Make sure we do not send RCS supported when we have not enumerated > it. > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 32c2053f2f08..acc4a3766dc1 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -433,7 +433,7 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc) > static void fill_engine_enable_masks(struct intel_gt *gt, > struct iosys_map *info_map) > { > - info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); > + info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); > info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 32c2053f2f08..acc4a3766dc1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -433,7 +433,7 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc) static void fill_engine_enable_masks(struct intel_gt *gt, struct iosys_map *info_map) { - info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); + info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt)); info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));