diff mbox series

drm/i915: Reduce stack usage in debugfs due to SSEU

Message ID 20220315020805.844962-1-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Reduce stack usage in debugfs due to SSEU | expand

Commit Message

Matt Roper March 15, 2022, 2:08 a.m. UTC
From: John Harrison <John.C.Harrison@Intel.com>

sseu_dev_info is already a pretty large structure which will likely
continue to grow when future platforms increase potential DSS and EU
counts.  Let's switch the stack placement of this structure in debugfs
with a dynamic allocation.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 22 +++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

Comments

Souza, Jose March 15, 2022, 4:19 p.m. UTC | #1
On Mon, 2022-03-14 at 19:08 -0700, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> sseu_dev_info is already a pretty large structure which will likely
> continue to grow when future platforms increase potential DSS and EU
> counts.  Let's switch the stack placement of this structure in debugfs
> with a dynamic allocation.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 22 +++++++++++++-------
>  1 file changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 6b944de48666..2d5d011e01db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -248,7 +248,7 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
>  {
>  	struct drm_i915_private *i915 = gt->i915;
>  	const struct intel_gt_info *info = &gt->info;
> -	struct sseu_dev_info sseu;
> +	struct sseu_dev_info *sseu;
>  	intel_wakeref_t wakeref;
>  
>  	if (GRAPHICS_VER(i915) < 8)
> @@ -258,23 +258,29 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
>  	i915_print_sseu_info(m, true, HAS_POOLED_EU(i915), &info->sseu);
>  
>  	seq_puts(m, "SSEU Device Status\n");
> -	memset(&sseu, 0, sizeof(sseu));
> -	intel_sseu_set_info(&sseu, info->sseu.max_slices,
> +
> +	sseu = kzalloc(sizeof(*sseu), GFP_KERNEL);
> +	if (!sseu)
> +		return -ENOMEM;
> +
> +	intel_sseu_set_info(sseu, info->sseu.max_slices,
>  			    info->sseu.max_subslices,
>  			    info->sseu.max_eus_per_subslice);
>  
>  	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>  		if (IS_CHERRYVIEW(i915))
> -			cherryview_sseu_device_status(gt, &sseu);
> +			cherryview_sseu_device_status(gt, sseu);
>  		else if (IS_BROADWELL(i915))
> -			bdw_sseu_device_status(gt, &sseu);
> +			bdw_sseu_device_status(gt, sseu);
>  		else if (GRAPHICS_VER(i915) == 9)
> -			gen9_sseu_device_status(gt, &sseu);
> +			gen9_sseu_device_status(gt, sseu);
>  		else if (GRAPHICS_VER(i915) >= 11)
> -			gen11_sseu_device_status(gt, &sseu);
> +			gen11_sseu_device_status(gt, sseu);
>  	}
>  
> -	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu);
> +	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), sseu);
> +
> +	kfree(sseu);
>  
>  	return 0;
>  }
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 6b944de48666..2d5d011e01db 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -248,7 +248,7 @@  int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
 	const struct intel_gt_info *info = &gt->info;
-	struct sseu_dev_info sseu;
+	struct sseu_dev_info *sseu;
 	intel_wakeref_t wakeref;
 
 	if (GRAPHICS_VER(i915) < 8)
@@ -258,23 +258,29 @@  int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
 	i915_print_sseu_info(m, true, HAS_POOLED_EU(i915), &info->sseu);
 
 	seq_puts(m, "SSEU Device Status\n");
-	memset(&sseu, 0, sizeof(sseu));
-	intel_sseu_set_info(&sseu, info->sseu.max_slices,
+
+	sseu = kzalloc(sizeof(*sseu), GFP_KERNEL);
+	if (!sseu)
+		return -ENOMEM;
+
+	intel_sseu_set_info(sseu, info->sseu.max_slices,
 			    info->sseu.max_subslices,
 			    info->sseu.max_eus_per_subslice);
 
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
 		if (IS_CHERRYVIEW(i915))
-			cherryview_sseu_device_status(gt, &sseu);
+			cherryview_sseu_device_status(gt, sseu);
 		else if (IS_BROADWELL(i915))
-			bdw_sseu_device_status(gt, &sseu);
+			bdw_sseu_device_status(gt, sseu);
 		else if (GRAPHICS_VER(i915) == 9)
-			gen9_sseu_device_status(gt, &sseu);
+			gen9_sseu_device_status(gt, sseu);
 		else if (GRAPHICS_VER(i915) >= 11)
-			gen11_sseu_device_status(gt, &sseu);
+			gen11_sseu_device_status(gt, sseu);
 	}
 
-	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu);
+	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), sseu);
+
+	kfree(sseu);
 
 	return 0;
 }