From patchwork Fri Mar 25 17:14:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 12791779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADA40C433FE for ; Fri, 25 Mar 2022 17:17:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6E0A810E8AE; Fri, 25 Mar 2022 17:17:10 +0000 (UTC) Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7D47710E74A for ; Fri, 25 Mar 2022 17:16:59 +0000 (UTC) Received: by mail-wr1-x434.google.com with SMTP id h23so11744435wrb.8 for ; Fri, 25 Mar 2022 10:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jrGtzUb1A9DfB89A9VTRS7pXkzrbTky760VebZOoHK0=; b=iQSrsH9BD/B641T27ogEpQH/ydFOoaJdiqKcbNEnBHC71WQgfBklLXsCO2WIbLIfHH SaGxrPOt/7Ecer7T5920AespR95oBeigGrtrdJdDoG+SGqZ87UyNwdAm16FA+7NVTIiQ W82/Fr7wrq68kVqdQCyQctxG3KuRVv4eaXEK9lycWy4wUztjAdlbKTCnIe6aB+M3LPx2 l7XXlSNBwzh6L6FOthayduEAjl1DSGgWG4DRiKUY0b6gdWCRvrbdv+BxHduUheVqyhto QNxPul63aBFuQMVCURI0sTYm6AGH1ZoEvBV+TlYdljbWGU/zc5m36a6wYy7BOw8DQYRv 575g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jrGtzUb1A9DfB89A9VTRS7pXkzrbTky760VebZOoHK0=; b=c9Bh9S9srHTzaxOosx/lWeBlslseWZLrg2dz3lGN3SbgmFZfyO3MZS13vpiFzve++t Hjhv+UhgDySqIpUNbcG7e+bkcGHuJjT1hS1Wl+mgO1vQx0gh/AcOLhek2JSRKL2zvb27 fPUTvh77IgL0qgpVvkm9ezMHB/GIDBgdEL2ffKKcXIlNw7P7LYXaTOpGc4Qef06QGA6d lOsEBqOkt/f8CWmYJs90DT9zpF/TdVZPkgrPzRwuuCm1v8Ks1Tr+xo3LkJQi+yWn5v0K h62S5BFpknuAZugglQnkm21XJ27ie9vAGrI0Hs93KLPfbSaqpCWhbXzmZ112xdyTBpmf EhJA== X-Gm-Message-State: AOAM532vrqjv8LMBa2GiSJtzI21jgMcupW3Hh/1Pn3/K457+n4Oum+AZ WkLDalVFJCbLDM+XJLvEM7ze/Q== X-Google-Smtp-Source: ABdhPJyr/MHqNoxrEZxkSxI69GzpBet5NWJv730TUb5gDeppIGg95/PkafvqVtTJGsSmjnsTffPwUA== X-Received: by 2002:a5d:47a6:0:b0:205:97fc:8e98 with SMTP id 6-20020a5d47a6000000b0020597fc8e98mr7810743wrb.103.1648228617894; Fri, 25 Mar 2022 10:16:57 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6240-cc41-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6240:cc41:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id p16-20020a5d6390000000b00203ffebddf3sm7547464wru.99.2022.03.25.10.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Mar 2022 10:16:57 -0700 (PDT) From: Guillaume Ranquet To: chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, matthias.bgg@gmail.com, chunfeng.yun@mediatek.com, kishon@ti.com, vkoul@kernel.org, deller@gmx.de, ck.hu@mediatek.com, jitao.shi@mediatek.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 07/22] drm/mediatek: dpi: move dpi limits to SoC config Date: Fri, 25 Mar 2022 18:14:56 +0100 Message-Id: <20220325171511.23493-8-granquet@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220325171511.23493-1-granquet@baylibre.com> References: <20220325171511.23493-1-granquet@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, markyacoub@google.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add flexibility by moving the dpi limits to the SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4554e2de1430..4746eb342567 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); - limit.c_bottom = 0x0010; - limit.c_top = 0x0FE0; - limit.y_bottom = 0x0010; - limit.y_top = 0x0FE0; - dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, }; +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { + .c_bottom = 0x0010, + .c_top = 0x0FE0, + .y_bottom = 0x0010, + .y_top = 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt2701_conf = { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8183_conf = { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8192_conf = { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static int mtk_dpi_probe(struct platform_device *pdev)