| Message ID | 20220407185617.179573-2-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] dt-bindings: display: bridge: icn6211: Document DSI data-lanes property | expand |
On Thu, 7 Apr 2022 at 20:56, Marek Vasut <marex@denx.de> wrote: > > The driver currently hard-codes DSI lane count to two, however the chip > is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT > property and program the result into DSI_CTRL register. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Jagan Teki <jagan@amarulasolutions.com> > Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Cc: Maxime Ripard <maxime@cerno.tech> > Cc: Robert Foss <robert.foss@linaro.org> > Cc: Sam Ravnborg <sam@ravnborg.org> > Cc: Thomas Zimmermann <tzimmermann@suse.de> > To: dri-devel@lists.freedesktop.org > --- > drivers/gpu/drm/bridge/chipone-icn6211.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c > index 6ce0633d4c089..e2b599a44275c 100644 > --- a/drivers/gpu/drm/bridge/chipone-icn6211.c > +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c > @@ -395,6 +395,11 @@ static void chipone_atomic_enable(struct drm_bridge *bridge, > /* dsi specific sequence */ > chipone_writeb(icn, SYNC_EVENT_DLY, 0x80); > chipone_writeb(icn, HFP_MIN, hfp & 0xff); > + > + /* DSI data lane count */ > + chipone_writeb(icn, DSI_CTRL, > + DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1)); > + > chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0); > chipone_writeb(icn, PLL_CTRL(12), 0xff); > chipone_writeb(icn, MIPI_PN_SWAP, 0x00); > @@ -480,9 +485,23 @@ static void chipone_mode_set(struct drm_bridge *bridge, > static int chipone_dsi_attach(struct chipone *icn) > { > struct mipi_dsi_device *dsi = icn->dsi; > - int ret; > + struct device *dev = icn->dev; > + struct device_node *endpoint; > + int dsi_lanes, ret; > + > + endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); > + dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); > + of_node_put(endpoint); > + > + /* > + * If the 'data-lanes' property does not exist in DT or is invalid, > + * default to previously hard-coded behavior, which was 4 data lanes. > + */ > + if (dsi_lanes >= 1 && dsi_lanes <= 4) > + icn->dsi->lanes = dsi_lanes; > + else > + icn->dsi->lanes = 4; > > - dsi->lanes = 4; > dsi->format = MIPI_DSI_FMT_RGB888; > dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; Reviewed-by: Robert Foss <robert.foss@linaro.org> Fixed checkpatch --strict format warning & applied to drm-misc-next. Rob.
diff --git a/drivers/gpu/drm/bridge/chipone-icn6211.c b/drivers/gpu/drm/bridge/chipone-icn6211.c index 6ce0633d4c089..e2b599a44275c 100644 --- a/drivers/gpu/drm/bridge/chipone-icn6211.c +++ b/drivers/gpu/drm/bridge/chipone-icn6211.c @@ -395,6 +395,11 @@ static void chipone_atomic_enable(struct drm_bridge *bridge, /* dsi specific sequence */ chipone_writeb(icn, SYNC_EVENT_DLY, 0x80); chipone_writeb(icn, HFP_MIN, hfp & 0xff); + + /* DSI data lane count */ + chipone_writeb(icn, DSI_CTRL, + DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1)); + chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0); chipone_writeb(icn, PLL_CTRL(12), 0xff); chipone_writeb(icn, MIPI_PN_SWAP, 0x00); @@ -480,9 +485,23 @@ static void chipone_mode_set(struct drm_bridge *bridge, static int chipone_dsi_attach(struct chipone *icn) { struct mipi_dsi_device *dsi = icn->dsi; - int ret; + struct device *dev = icn->dev; + struct device_node *endpoint; + int dsi_lanes, ret; + + endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); + dsi_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); + of_node_put(endpoint); + + /* + * If the 'data-lanes' property does not exist in DT or is invalid, + * default to previously hard-coded behavior, which was 4 data lanes. + */ + if (dsi_lanes >= 1 && dsi_lanes <= 4) + icn->dsi->lanes = dsi_lanes; + else + icn->dsi->lanes = 4; - dsi->lanes = 4; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
The driver currently hard-codes DSI lane count to two, however the chip is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT property and program the result into DSI_CTRL register. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Robert Foss <robert.foss@linaro.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> To: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/bridge/chipone-icn6211.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-)