| Message ID | 20220408180326.1454951-4-John.C.Harrison@Intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update to GuC v70 | expand |
On 4/8/2022 11:03 AM, John.C.Harrison@Intel.com wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > Update to the latest GuC firmware release. > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > --- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++++++++++++------------ > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index bb864655c495..cb5dd16421d0 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -53,22 +53,22 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, > * firmware as TGL. > */ > #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ > - fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ > - fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ > - fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ > - fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \ > - fw_def(ROCKETLAKE, 0, guc_def(tgl, 69, 0, 3)) \ > - fw_def(TIGERLAKE, 0, guc_def(tgl, 69, 0, 3)) \ > - fw_def(JASPERLAKE, 0, guc_def(ehl, 69, 0, 3)) \ > - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 69, 0, 3)) \ > - fw_def(ICELAKE, 0, guc_def(icl, 69, 0, 3)) \ > - fw_def(COMETLAKE, 5, guc_def(cml, 69, 0, 3)) \ > - fw_def(COMETLAKE, 0, guc_def(kbl, 69, 0, 3)) \ > - fw_def(COFFEELAKE, 0, guc_def(kbl, 69, 0, 3)) \ > - fw_def(GEMINILAKE, 0, guc_def(glk, 69, 0, 3)) \ > - fw_def(KABYLAKE, 0, guc_def(kbl, 69, 0, 3)) \ > - fw_def(BROXTON, 0, guc_def(bxt, 69, 0, 3)) \ > - fw_def(SKYLAKE, 0, guc_def(skl, 69, 0, 3)) > + fw_def(DG2, 0, guc_def(dg2, 70, 1, 1)) \ > + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 70, 1, 1)) \ > + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 70, 1, 1)) \ > + fw_def(DG1, 0, guc_def(dg1, 70, 1, 1)) \ > + fw_def(ROCKETLAKE, 0, guc_def(tgl, 70, 1, 1)) \ > + fw_def(TIGERLAKE, 0, guc_def(tgl, 70, 1, 1)) \ > + fw_def(JASPERLAKE, 0, guc_def(ehl, 70, 1, 1)) \ > + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 70, 1, 1)) \ > + fw_def(ICELAKE, 0, guc_def(icl, 70, 1, 1)) \ > + fw_def(COMETLAKE, 5, guc_def(cml, 70, 1, 1)) \ > + fw_def(COMETLAKE, 0, guc_def(kbl, 70, 1, 1)) \ > + fw_def(COFFEELAKE, 0, guc_def(kbl, 70, 1, 1)) \ > + fw_def(GEMINILAKE, 0, guc_def(glk, 70, 1, 1)) \ > + fw_def(KABYLAKE, 0, guc_def(kbl, 70, 1, 1)) \ > + fw_def(BROXTON, 0, guc_def(bxt, 70, 1, 1)) \ > + fw_def(SKYLAKE, 0, guc_def(skl, 70, 1, 1)) > > #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ > fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index bb864655c495..cb5dd16421d0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -53,22 +53,22 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * firmware as TGL. */ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ - fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \ - fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \ - fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \ - fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \ - fw_def(ROCKETLAKE, 0, guc_def(tgl, 69, 0, 3)) \ - fw_def(TIGERLAKE, 0, guc_def(tgl, 69, 0, 3)) \ - fw_def(JASPERLAKE, 0, guc_def(ehl, 69, 0, 3)) \ - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 69, 0, 3)) \ - fw_def(ICELAKE, 0, guc_def(icl, 69, 0, 3)) \ - fw_def(COMETLAKE, 5, guc_def(cml, 69, 0, 3)) \ - fw_def(COMETLAKE, 0, guc_def(kbl, 69, 0, 3)) \ - fw_def(COFFEELAKE, 0, guc_def(kbl, 69, 0, 3)) \ - fw_def(GEMINILAKE, 0, guc_def(glk, 69, 0, 3)) \ - fw_def(KABYLAKE, 0, guc_def(kbl, 69, 0, 3)) \ - fw_def(BROXTON, 0, guc_def(bxt, 69, 0, 3)) \ - fw_def(SKYLAKE, 0, guc_def(skl, 69, 0, 3)) + fw_def(DG2, 0, guc_def(dg2, 70, 1, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 70, 1, 1)) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 70, 1, 1)) \ + fw_def(DG1, 0, guc_def(dg1, 70, 1, 1)) \ + fw_def(ROCKETLAKE, 0, guc_def(tgl, 70, 1, 1)) \ + fw_def(TIGERLAKE, 0, guc_def(tgl, 70, 1, 1)) \ + fw_def(JASPERLAKE, 0, guc_def(ehl, 70, 1, 1)) \ + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 70, 1, 1)) \ + fw_def(ICELAKE, 0, guc_def(icl, 70, 1, 1)) \ + fw_def(COMETLAKE, 5, guc_def(cml, 70, 1, 1)) \ + fw_def(COMETLAKE, 0, guc_def(kbl, 70, 1, 1)) \ + fw_def(COFFEELAKE, 0, guc_def(kbl, 70, 1, 1)) \ + fw_def(GEMINILAKE, 0, guc_def(glk, 70, 1, 1)) \ + fw_def(KABYLAKE, 0, guc_def(kbl, 70, 1, 1)) \ + fw_def(BROXTON, 0, guc_def(bxt, 70, 1, 1)) \ + fw_def(SKYLAKE, 0, guc_def(skl, 70, 1, 1)) #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \ fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \