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Thu, 14 Apr 2022 06:47:43 +0000 From: Liu Ying To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 3/5] dt-bindings: phy: Convert mixel, mipi-dsi-phy to json-schema Date: Thu, 14 Apr 2022 14:48:56 +0800 Message-Id: <20220414064858.405096-4-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414064858.405096-1-victor.liu@nxp.com> References: <20220414064858.405096-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR06CA0005.apcprd06.prod.outlook.com (2603:1096:4:186::12) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bb1a901b-4c27-45fe-f14d-08da1de2ace7 X-MS-TrafficTypeDiagnostic: AM6PR04MB4744:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3OjWEkhC/qyPAwg1Jhm3gHT4niLiXVkxAYgE5NT1nA/iR6L7qkNbsIjqdxci0qP82d4L/WmbeLfj/oQqzrtlskFW1WQUYXk62kvL0myi3f8987bMIrc1Lslgcpck6M2OiFoAoDFVMNGPDGQ2PKWdCB0kimeioynQo9eBLO3jszTPmizqsCkSPzte8D1YCczRsEPFJKH8SgwiS5qg8LylaloOH6JjorZ/58lPhn+JIBkWtITRRY1So4n/djC10YX5sIOte4AWrOMpXBAm82YwCHU+nZ3b9zEhp9gnwh5GhHSfOpBKuLjLjQVStaT2aCgQLbwpapkZOqPtlFbixGxtv5JawPdwXNlBcri9qxdHFOi6uFJ1Due7PyIau+KCV96olRqrzotK2REM00lTi+xkw+IKN2OEe0e/AFM9p8Q7g+/MVrwF/wNWY/68rBHFc8petcwzDFsyHtdf/ma13dHJfd7iYJi0UdTk1Y2aekiZlOWriuMqAY/8cskKbgjomgTay/Tr4CTnG4u4Qf+6EUXpShsr5893sBNN9pET7wZBSBsMi4DRV/WZETMG2m/dPZO3Cj8stDM/CHTVRIBr2C4UG8OubINXQzzkIQR4CByXHPmQPTS5sX9CQatFhvgyHPUXJoHKYb+oQM4sNvBcj/mn6qfjOEaRl+KsF0Qj3qFGBv/dh/+VbfYBlXmpCVYkuyNp+UMXmvjyChUUIk6WF1M03iCB0SrDpKEK/FPKs1V9+ySwF9MaavFDGUJpkX/So5pEhx+GQnD3OTUdQneWz+LDfTglk7eBT3+TvCsi0av9MnLQW/jdmBQ+3uruKqbvW+o6Tl6PewxfiMbkfPJKdC7aNg== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Comparing to the plain text version, the new binding adds the 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' properites, otherwise 'make dtbs_check' would complain that there are mis-matches. Also, the new binding requires the 'power-domains' property since all potential SoCs that embed this PHY would provide a power domain for it. The example of the new binding takes reference to the latest dphy node in imx8mq.dtsi. Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Reviewed-by: Rob Herring Reviewed-by: Guido Günther Signed-off-by: Liu Ying --- v6->v7: * No change. v5->v6: * No change. v4->v5: * No change. v3->v4: * Add Rob's and Guido's R-b tags. v2->v3: * Improve the 'clock-names' property by dropping 'items:'. v1->v2: * Newly introduced in v2. (Guido) .../bindings/phy/mixel,mipi-dsi-phy.txt | 29 -------- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 72 +++++++++++++++++++ 2 files changed, 72 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt deleted file mode 100644 index 9b23407233c0..000000000000 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt +++ /dev/null @@ -1,29 +0,0 @@ -Mixel DSI PHY for i.MX8 - -The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the -MIPI-DSI IP from Northwest Logic). It represents the physical layer for the -electrical signals for DSI. - -Required properties: -- compatible: Must be: - - "fsl,imx8mq-mipi-dphy" -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "phy_ref": phandle and specifier referring to the DPHY ref clock -- reg: the register range of the PHY controller -- #phy-cells: number of cells in PHY, as defined in - Documentation/devicetree/bindings/phy/phy-bindings.txt - this must be <0> - -Optional properties: -- power-domains: phandle to power domain - -Example: - dphy: dphy@30a0030 { - compatible = "fsl,imx8mq-mipi-dphy"; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - reg = <0x30a00300 0x100>; - power-domains = <&pd_mipi0>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml new file mode 100644 index 000000000000..c34f2e6d6bd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel DSI PHY for i.MX8 + +maintainers: + - Guido Günther + +description: | + The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the + MIPI-DSI IP from Northwest Logic). It represents the physical layer for the + electrical signals for DSI. + +properties: + compatible: + enum: + - fsl,imx8mq-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: phy_ref + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include + dphy: dphy@30a0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + reg = <0x30a00300 0x100>; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&pgc_mipi>; + };