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Thu, 14 Apr 2022 07:09:24 +0000 From: Liu Ying To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v8 4/5] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp Date: Thu, 14 Apr 2022 15:10:38 +0800 Message-Id: <20220414071039.423271-5-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220414071039.423271-1-victor.liu@nxp.com> References: <20220414071039.423271-1-victor.liu@nxp.com> X-ClientProxiedBy: SI2PR06CA0005.apcprd06.prod.outlook.com (2603:1096:4:186::12) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 193c7933-d7ec-40f1-d10b-08da1de5b4d5 X-MS-TrafficTypeDiagnostic: AM5PR04MB3027:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8gSz5/KyecXHYKcsl7nMpCQ0wXTRZjIVqrQ4jtOkGm+VB1S0JHUjZG01Vkv6oRsLdf1IKISNZLHFYphovH4L5JLOZKjaNVaX70Smm/8qFjjhy9vwAE4y31obbPUep4JXFPXsR6XYHQBPsxU3wObYDJyAZl1CDKVobgnaXKfW5aDGiXbS58nvaA2vt1BlqdTTO6kXRGqRPvOBTZd9n5P+04r6n/fIOgRqueEvtZsNjuo7tNY7GHNM0zFN+lH4rc+iWR1hFaowYlRNW9JxibHAkW88MvfEm7TBoj087vZ14qYsLRj5ua3WdqELPcMWDKwP3VmShYyR2Psc+0OydoR/sX+uhZCubrxVqTEvdhEAxA7t3+iHjkKOj9iMj6PzE/AefZtasZ8/YNVeaADSLoYJx3oHaD8jhKw8oHoE8rFwSU7AE9K07ZDMixKi6pfBaca7CV17kQceA+FOPpvbBWrut2eyvMKFhRkFc96Y3tbr9VdSme0MbtPBwNW6FiNBtxFN4gzSpB8DqWbdK/oAgbVLXvQgPQE1Vx7Z65R281E9auo8pkPchFgIduacFWXLFKpJlmX63C6v1um7Q0gpjB+N65w4RjZXFThpqxcKLdJDEwOquoOF1NM42IMw9t/fSR046yQ0E0X4gi6pymTMDNdKViuHhCPxKTRiFwEdMyi/sAXtwARTleyv2GXm5ngdAzbQXjuuHHrMiqybwDvJLu07Bw== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Reviewed-by: Rob Herring Reviewed-by: Guido Günther Signed-off-by: Liu Ying --- v7->v8: * No change. v6->v7: * No change. v5->v6: * No change. v4->v5: * No change. v3->v4: * Add Rob's and Guido's R-b tags. v2->v3: * No change. v1->v2: * Add the binding for i.MX8qxp Mixel combo PHY based on the converted binding. (Guido) .../bindings/phy/mixel,mipi-dsi-phy.yaml | 41 +++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml index c34f2e6d6bd5..786cfd71cb7e 100644 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -14,10 +14,14 @@ description: | MIPI-DSI IP from Northwest Logic). It represents the physical layer for the electrical signals for DSI. + The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work + in either MIPI-DSI PHY mode or LVDS PHY mode. + properties: compatible: enum: - fsl,imx8mq-mipi-dphy + - fsl,imx8qxp-mipi-dphy reg: maxItems: 1 @@ -40,6 +44,11 @@ properties: "#phy-cells": const: 0 + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + power-domains: maxItems: 1 @@ -48,12 +57,38 @@ required: - reg - clocks - clock-names - - assigned-clocks - - assigned-clock-parents - - assigned-clock-rates - "#phy-cells" - power-domains +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-mipi-dphy + then: + properties: + fsl,syscon: false + + required: + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-dphy + then: + properties: + assigned-clocks: false + assigned-clock-parents: false + assigned-clock-rates: false + + required: + - fsl,syscon + additionalProperties: false examples: