From patchwork Thu Apr 28 10:53:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TmFuY3kgTGluICjmnpfmrKPonqIp?= X-Patchwork-Id: 12830458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCA68C433F5 for ; Thu, 28 Apr 2022 10:55:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D1C1F10FA4D; Thu, 28 Apr 2022 10:55:49 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 024FC10E927 for ; Thu, 28 Apr 2022 10:54:17 +0000 (UTC) X-UUID: a5811ab18c584a779edfeb16e8383a8b-20220428 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:beb64fd3-2a11-4e77-9875-0667d47ea0b4, OB:10, L OB:10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham ,ACTION:release,TS:75 X-CID-INFO: VERSION:1.1.4, REQID:beb64fd3-2a11-4e77-9875-0667d47ea0b4, OB:10, LOB :10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9, CLOUDID:5bed0a2f-6199-437e-8ab4-9920b4bc5b76, C OID:18557e12204f,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: a5811ab18c584a779edfeb16e8383a8b-20220428 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 36724993; Thu, 28 Apr 2022 18:54:13 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 28 Apr 2022 18:54:12 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 28 Apr 2022 18:54:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 28 Apr 2022 18:54:12 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , Subject: [PATCH v18 07/21] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Date: Thu, 28 Apr 2022 18:53:54 +0800 Message-ID: <20220428105408.11189-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220428105408.11189-1-nancy.lin@mediatek.com> References: <20220428105408.11189-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Yongqiang Niu , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nathan Chancellor , "Nancy . Lin" , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Modify mmsys for support 64 bit and different reset base. Add the number of reset bits in mmsys private data and move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 39 ++++++++++++++++++----------- drivers/soc/mediatek/mtk-mmsys.h | 1 + 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 5469073e3073..0a286fa5a824 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -139,6 +139,7 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +#define MT8195_VDO1_SW0_RST_B 0x1d0 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 #define MT8195_VDO1_HDR_TOP_CFG 0xd00 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 0315813b7df6..5fae31e3316f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -20,6 +20,8 @@ #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -86,6 +88,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = { @@ -100,6 +103,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = { @@ -114,6 +118,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .routes = mmsys_mt8186_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = { @@ -148,6 +153,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .clk_driver = "clk-mt8195-vdo1", .routes = mmsys_mt8195_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, + .num_resets = 64, }; static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = { @@ -234,18 +241,22 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; u32 reg; + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset + offset); if (assert) reg &= ~BIT(id); else reg |= BIT(id); - writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset + offset); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -358,18 +369,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - spin_lock_init(&mmsys->lock); - - mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; - mmsys->rcdev.of_node = pdev->dev.of_node; - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); - if (ret) { - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); - return ret; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "Couldn't get mmsys resource\n"); @@ -391,6 +390,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev) mmsys->data = match_data->drv_data[0]; } + spin_lock_init(&mmsys->lock); + + mmsys->rcdev.owner = THIS_MODULE; + mmsys->rcdev.nr_resets = mmsys->data->num_resets; + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; + mmsys->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); + if (ret) { + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); + return ret; + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index f01ba206481d..20a271b80b3b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -92,6 +92,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u32 num_resets; }; struct mtk_mmsys_match_data {