| Message ID | 20220501195620.4135080-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clock | expand |
Quoting Dmitry Baryshkov (2022-05-01 12:56:20) > Remove dividers that are not recommended for DSI DPHY mode when setting Is "DPHY" intentional or just "PHY" should be here? > up the clock tree for the DSI pixel clock. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 6e506feb111f..66ed1919a1db 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide > snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); > snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); > snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); > - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); > - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); > > hw = devm_clk_hw_register_mux(dev, clk_name, > ((const char *[]){ > - parent, parent2, parent3, parent4 > - }), 4, 0, pll_7nm->phy->base + > + parent, parent2, > + }), 2, 0, pll_7nm->phy->base + > REG_DSI_7nm_PHY_CMN_CLK_CFG1, > - 0, 2, 0, NULL); > + 0, 1, 0, NULL); Can you followup with a patch to move to clk_parent_data instead of strings?
On 2022-05-02 13:47:51, Stephen Boyd wrote: > Quoting Dmitry Baryshkov (2022-05-01 12:56:20) > > Remove dividers that are not recommended for DSI DPHY mode when setting > > Is "DPHY" intentional or just "PHY" should be here? > > > up the clock tree for the DSI pixel clock. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > > index 6e506feb111f..66ed1919a1db 100644 > > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > > @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide > > snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); > > snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); > > snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); > > - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); > > - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); > > > > hw = devm_clk_hw_register_mux(dev, clk_name, > > ((const char *[]){ > > - parent, parent2, parent3, parent4 > > - }), 4, 0, pll_7nm->phy->base + > > + parent, parent2, > > + }), 2, 0, pll_7nm->phy->base + > > REG_DSI_7nm_PHY_CMN_CLK_CFG1, > > - 0, 2, 0, NULL); > > + 0, 1, 0, NULL); > > Can you followup with a patch to move to clk_parent_data instead of > strings? Dmitry and I discussed this a while ago, and I actually have patches in progress converting this. Dmitry, if you haven't started on the conversion yet, perhaps it's efficient if I respin my efforts and submit them soon? - Marijn
On 03/05/2022 00:42, Marijn Suijten wrote: > On 2022-05-02 13:47:51, Stephen Boyd wrote: >> Quoting Dmitry Baryshkov (2022-05-01 12:56:20) >>> Remove dividers that are not recommended for DSI DPHY mode when setting >> >> Is "DPHY" intentional or just "PHY" should be here? >> >>> up the clock tree for the DSI pixel clock. >>> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >> >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------ >>> 1 file changed, 4 insertions(+), 6 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> index 6e506feb111f..66ed1919a1db 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide >>> snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); >>> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); >>> snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); >>> - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); >>> - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); >>> >>> hw = devm_clk_hw_register_mux(dev, clk_name, >>> ((const char *[]){ >>> - parent, parent2, parent3, parent4 >>> - }), 4, 0, pll_7nm->phy->base + >>> + parent, parent2, >>> + }), 2, 0, pll_7nm->phy->base + >>> REG_DSI_7nm_PHY_CMN_CLK_CFG1, >>> - 0, 2, 0, NULL); >>> + 0, 1, 0, NULL); >> >> Can you followup with a patch to move to clk_parent_data instead of >> strings? > > Dmitry and I discussed this a while ago, and I actually have patches in > progress converting this. Dmitry, if you haven't started on the > conversion yet, perhaps it's efficient if I respin my efforts and submit > them soon? Yes, please. I'm under the pile of other things. Your patches will be appreciated. You don't have to convert all PHYs at once.
On 2022-05-03 01:02:42, Dmitry Baryshkov wrote: > On 03/05/2022 00:42, Marijn Suijten wrote: > > On 2022-05-02 13:47:51, Stephen Boyd wrote: > >> Quoting Dmitry Baryshkov (2022-05-01 12:56:20) > >>> Remove dividers that are not recommended for DSI DPHY mode when setting > >> > >> Is "DPHY" intentional or just "PHY" should be here? > >> > >>> up the clock tree for the DSI pixel clock. > >>> > >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >>> --- > >> > >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> > >> > >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------ > >>> 1 file changed, 4 insertions(+), 6 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >>> index 6e506feb111f..66ed1919a1db 100644 > >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > >>> @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide > >>> snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); > >>> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); > >>> snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); > >>> - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); > >>> - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); > >>> > >>> hw = devm_clk_hw_register_mux(dev, clk_name, > >>> ((const char *[]){ > >>> - parent, parent2, parent3, parent4 > >>> - }), 4, 0, pll_7nm->phy->base + > >>> + parent, parent2, > >>> + }), 2, 0, pll_7nm->phy->base + > >>> REG_DSI_7nm_PHY_CMN_CLK_CFG1, > >>> - 0, 2, 0, NULL); > >>> + 0, 1, 0, NULL); > >> > >> Can you followup with a patch to move to clk_parent_data instead of > >> strings? > > > > Dmitry and I discussed this a while ago, and I actually have patches in > > progress converting this. Dmitry, if you haven't started on the > > conversion yet, perhaps it's efficient if I respin my efforts and submit > > them soon? > > Yes, please. I'm under the pile of other things. Your patches will be > appreciated. You don't have to convert all PHYs at once. Holding to my promise, the patches are now available on the lists: https://lore.kernel.org/linux-arm-msm/20220523213837.1016542-1-marijn.suijten@somainline.org/T/#t It was more convenient to convert the remaining PHYs on top of the 14/28nm I had already done, it's mostly trivial work anyway. - Marijn
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 6e506feb111f..66ed1919a1db 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -586,7 +586,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) { char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; + char parent2[32]; struct clk_init_data vco_init = { .parent_data = &(const struct clk_parent_data) { .fw_name = "ref", @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_7nm->phy->base + + parent, parent2, + }), 2, 0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); + 0, 1, 0, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail;
Remove dividers that are not recommended for DSI DPHY mode when setting up the clock tree for the DSI pixel clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)