[v19,10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1

Commit Message

Nancy Lin (林欣螢) May 3, 2022, 10:23 a.m. UTC

MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Add the number of reset bits and reset base in mmsys
private data.

Signed-off-by: Nancy.Lin <[e-mail]>
Reviewed-by: AngeloGioacchino Del Regno <[e-mail]>
---
 drivers/soc/mediatek/mt8195-mmsys.h | 1 +
 drivers/soc/mediatek/mtk-mmsys.c    | 2 ++
 2 files changed, 3 insertions(+)

Comments

CK Hu (胡俊光) May 4, 2022, 5:37 a.m. UTC | #1

Hi, Nancy:

On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Add the number of reset bits and reset base in
> mmsys
> private data.

Reviewed-by: CK Hu <[e-mail]>

> 
> Signed-off-by: Nancy.Lin <[e-mail]>
> Reviewed-by: AngeloGioacchino Del Regno <
> [e-mail]>
> ---
>  drivers/soc/mediatek/mt8195-mmsys.h | 1 +
>  drivers/soc/mediatek/mtk-mmsys.c    | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> b/drivers/soc/mediatek/mt8195-mmsys.h
> index 454944a9409c..a6652ae63431 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,7 @@
>  #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 <<
> 16)
>  #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> (3 << 16)
>  
> +#define MT8195_VDO1_SW0_RST_B					
> 0x1d0
>  #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD				
> 0xe30
>  #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD				
> 0xe70
>  #define MT8195_VDO1_HDR_TOP_CFG					
> 0xd00
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 6600185dd9a4..d6ea1b0ac2de 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -153,6 +153,8 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys1_driver_data = {
>  	.clk_driver = "clk-mt8195-vdo1",
>  	.routes = mmsys_mt8195_vdo1_routing_table,
>  	.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
> +	.sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
> +	.num_resets = 64,
>  };
>  
>  static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {

Patch

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 454944a9409c..a6652ae63431 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -75,6 +75,7 @@ 
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
 
+#define MT8195_VDO1_SW0_RST_B					0x1d0
 #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD				0xe30
 #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD				0xe70
 #define MT8195_VDO1_HDR_TOP_CFG					0xd00
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 6600185dd9a4..d6ea1b0ac2de 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -153,6 +153,8 @@  static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.clk_driver = "clk-mt8195-vdo1",
 	.routes = mmsys_mt8195_vdo1_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table),
+	.sw0_rst_offset = MT8195_VDO1_SW0_RST_B,
+	.num_resets = 64,
 };
 
 static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {