diff mbox series

drm/i915/dg2: Correct DSS check for Wa_1308578152

Message ID 20220607154724.3155521-1-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dg2: Correct DSS check for Wa_1308578152 | expand

Commit Message

Matt Roper June 7, 2022, 3:47 p.m. UTC
When converting our DSS masks to bitmaps, we fumbled the condition used
to check whether any DSS are present in the first gslice.  Since
intel_sseu_find_first_xehp_dss() returns a 0-based number, we need a >=
condition rather than >.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Reported-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Balasubramani Vivekanandan June 7, 2022, 4:07 p.m. UTC | #1
On 07.06.2022 08:47, Matt Roper wrote:
> When converting our DSS masks to bitmaps, we fumbled the condition used
> to check whether any DSS are present in the first gslice.  Since
> intel_sseu_find_first_xehp_dss() returns a 0-based number, we need a >=
> condition rather than >.
> 
> Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
> Reported-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 1b191b234160..67104ba8951e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2079,7 +2079,7 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  
>  static bool needs_wa_1308578152(struct intel_engine_cs *engine)
>  {
> -	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> +	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
>  		GEN_DSS_PER_GSLICE;
>  }

Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>  
> -- 
> 2.35.3
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b191b234160..67104ba8951e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2079,7 +2079,7 @@  engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
 {
-	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+	return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
 		GEN_DSS_PER_GSLICE;
 }