diff mbox series

drm/i915/xehp: Correct steering initialization

Message ID 20220607175716.3338661-1-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/xehp: Correct steering initialization | expand

Commit Message

Matt Roper June 7, 2022, 5:57 p.m. UTC
Another mistake during the conversion to DSS bitmaps:  after retrieving
the DSS ID intel_sseu_find_first_xehp_dss() we forgot to modulo it down
to obtain which ID within the current gslice it is.

Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Balasubramani Vivekanandan June 8, 2022, 8:46 a.m. UTC | #1
On 07.06.2022 10:57, Matt Roper wrote:
> Another mistake during the conversion to DSS bitmaps:  after retrieving
> the DSS ID intel_sseu_find_first_xehp_dss() we forgot to modulo it down
> to obtain which ID within the current gslice it is.
> 
> Fixes: b87d39019651 ("drm/i915/sseu: Disassociate internal subslice mask representation from uapi")
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b7421f109c13..a5c0508c5b63 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1177,8 +1177,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
>  	}
>  
>  	slice = __ffs(slice_mask);
> -	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> -	WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> +	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
> +		GEN_DSS_PER_GSLICE;

Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>  
>  	__add_mcr_wa(gt, wal, slice, subslice);
>  
> -- 
> 2.35.3
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b7421f109c13..a5c0508c5b63 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1177,8 +1177,8 @@  xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
 	}
 
 	slice = __ffs(slice_mask);
-	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
-	WARN_ON(subslice > GEN_DSS_PER_GSLICE);
+	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
+		GEN_DSS_PER_GSLICE;
 
 	__add_mcr_wa(gt, wal, slice, subslice);