| Message ID | 20220608005108.3717895-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: More PVC+DG2 workarounds | expand |
> -----Original Message----- > From: Roper, Matthew D <matthew.d.roper@intel.com> > Sent: Wednesday, June 8, 2022 6:21 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Roper, Matthew D > <matthew.d.roper@intel.com>; Gupta, Anshuman > <anshuman.gupta@intel.com>; Nilawar, Badal <badal.nilawar@intel.com>; > Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com> > Subject: [PATCH] drm/i915: More PVC+DG2 workarounds > > A new PVC+DG2 workaround has appeared recently: > - Wa_16015675438 > > And a couple existing DG2 workarounds have been extended to PVC: > - Wa_14015795083 > - Wa_18018781329 Looks good to me. Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Regards, Anshuman Gupta. > > Note that Wa_16015675438 asks us to program a register that is in the 0x2xxx > range typically associated with the RCS engine, even though PVC does not have > an RCS. By default the GuC will think we've made a mistake and throw an > exception when it sees this register on a CCS engine's save/restore list, so we > need to pass an extra GuC control flag to tell it that this is expected and not a > problem. > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++++------ > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + > 4 files changed, 23 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index c8129a351731..226557018037 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -140,6 +140,7 @@ > #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) > #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) > #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) > +#define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) > > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) > #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 1e7ca3863f20..e1e70eff9aac 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1491,13 +1491,20 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct > i915_wa_list *wal) > wa_write_clr(wal, GEN7_MISCCPCTL, > GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > } > > +static void > +pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > +{ > + /* Wa_14015795083 */ > + wa_write_clr(wal, GEN7_MISCCPCTL, > GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > +} > + > static void > gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) { > struct drm_i915_private *i915 = gt->i915; > > if (IS_PONTEVECCHIO(i915)) > - ; /* none yet */ > + pvc_gt_workarounds_init(gt, wal); > else if (IS_DG2(i915)) > dg2_gt_workarounds_init(gt, wal); > else if (IS_XEHPSDV(i915)) > @@ -2082,12 +2089,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > * performance guide section. > */ > wa_write_or(wal, XEHP_L3SCQREG7, > BLEND_FILL_CACHING_OPT_DIS); > - > - /* Wa_18018781329:dg2 */ > - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); > - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); > - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); > } > > if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { @@ - > 2700,6 +2701,15 @@ general_render_compute_wa_init(struct intel_engine_cs > *engine, struct i915_wa_li > > /* Wa_22014226127:dg2,pvc */ > wa_write_or(wal, LSC_CHICKEN_BIT_0, > DISABLE_D8_D16_COASLESCE); > + > + /* Wa_16015675438:dg2,pvc */ > + wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, > +GEN12_PERF_FIX_BALANCING_CFE_DISABLE); > + > + /* Wa_18018781329:dg2,pvc */ > + wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); > + wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > + wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); > + wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); > } > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 2c4ad4a65089..35887cb53201 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -327,6 +327,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) > flags |= GUC_WA_CONTEXT_ISOLATION; > > + /* Wa_16015675438 */ > + if (!RCS_MASK(gt)) > + flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; > + > return flags; > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > index 42cb7a9a6199..b3c9a9327f76 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > @@ -105,6 +105,7 @@ > #define GUC_WA_PRE_PARSER BIT(14) > #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) > #define GUC_WA_POLLCS BIT(18) > +#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21) > > #define GUC_CTL_FEATURE 2 > #define GUC_CTL_ENABLE_SLPC BIT(2) > -- > 2.35.3
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index c8129a351731..226557018037 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -140,6 +140,7 @@ #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) +#define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1e7ca3863f20..e1e70eff9aac 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1491,13 +1491,20 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); } +static void +pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) +{ + /* Wa_14015795083 */ + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); +} + static void gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; if (IS_PONTEVECCHIO(i915)) - ; /* none yet */ + pvc_gt_workarounds_init(gt, wal); else if (IS_DG2(i915)) dg2_gt_workarounds_init(gt, wal); else if (IS_XEHPSDV(i915)) @@ -2082,12 +2089,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * performance guide section. */ wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); - - /* Wa_18018781329:dg2 */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); } if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { @@ -2700,6 +2701,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li /* Wa_22014226127:dg2,pvc */ wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); + + /* Wa_16015675438:dg2,pvc */ + wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); + + /* Wa_18018781329:dg2,pvc */ + wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); } } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 2c4ad4a65089..35887cb53201 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -327,6 +327,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) flags |= GUC_WA_CONTEXT_ISOLATION; + /* Wa_16015675438 */ + if (!RCS_MASK(gt)) + flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; + return flags; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index 42cb7a9a6199..b3c9a9327f76 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -105,6 +105,7 @@ #define GUC_WA_PRE_PARSER BIT(14) #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) #define GUC_WA_POLLCS BIT(18) +#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21) #define GUC_CTL_FEATURE 2 #define GUC_CTL_ENABLE_SLPC BIT(2)