From patchwork Sat Jul 9 05:59:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12912107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 357E9CCA47C for ; Sat, 9 Jul 2022 06:00:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3553410EC7F; Sat, 9 Jul 2022 06:00:27 +0000 (UTC) Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by gabe.freedesktop.org (Postfix) with ESMTPS id 25F5810EC81; Sat, 9 Jul 2022 06:00:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657346426; x=1688882426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=XGQbLWmmXvctI4HYl9j46qsii5iPHrQ4eKepFp+Nbs8=; b=OdQHJC8yKH6jBT/zlTck0m0ZDpbvAJyvsVTefw+poRF+R9Z00G5VabFc PB81/Utpv6LKjNDlz71qm83ChC+vEAK3Nod9DD20DEUzyZlu81nooxFcP uJlAoo7xXyGwP3udbBH1M6coVQX7g6/luBN6PFUUnc5SAEAHGJBQQWok6 4=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Jul 2022 23:00:25 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2022 23:00:24 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 8 Jul 2022 23:00:24 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 8 Jul 2022 23:00:18 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson Subject: [PATCH v2 4/7] drm/msm: Ensure cx gdsc collapse during recovery Date: Sat, 9 Jul 2022 11:29:32 +0530 Message-ID: <20220709112837.v2.4.I510084ecc82b2efe42dd904fea595cdec99058b2@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1657346375-1461-1-git-send-email-quic_akhilpo@quicinc.com> References: <1657346375-1461-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , Akhil P Oommen , linux-kernel@vger.kernel.org, Stephen Boyd , Konrad Dybcio , Abhinav Kumar , Douglas Anderson , David Airlie , Matthias Kaehlcke , Dmitry Baryshkov , Jordan Crouse , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To improve our chance of a successful recovery, we should ensure that cx headswitch collapses. Cx headswitch might be kept enabled through a vote from another driver like iommu or even another hardware subsystem. So, poll the cx gdscr register to ensure that it collapses during recovery. Signed-off-by: Akhil P Oommen --- (no changes since v1) drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 ++++++++++++- drivers/gpu/drm/msm/msm_gpu.c | 4 ++++ drivers/gpu/drm/msm/msm_gpu.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7ed347c..9aaa469 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1257,11 +1257,15 @@ static void a6xx_dump(struct msm_gpu *gpu) #define VBIF_RESET_ACK_TIMEOUT 100 #define VBIF_RESET_ACK_MASK 0x00f0 +#define CX_GDSCR_OFFSET 0x106c +#define CX_GDSC_ON_MASK BIT(31) + static void a6xx_recover(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - int i; + int i, ret; + u32 val; adreno_dump_info(gpu); @@ -1288,6 +1292,13 @@ static void a6xx_recover(struct msm_gpu *gpu) /* And the final one from recover worker */ pm_runtime_put_sync(&gpu->pdev->dev); + if (gpu->gpucc_io) { + ret = readl_poll_timeout(gpu->gpucc_io + CX_GDSCR_OFFSET, val, + !(val & CX_GDSC_ON_MASK), 100, 500000); + if (ret) + DRM_DEV_INFO(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); + } + for (i = gpu->active_submits; i > 0; i--) pm_runtime_get(&gpu->pdev->dev); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index aa6f34f..7ada0785 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -865,6 +865,10 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, goto fail; } + gpu->gpucc_io = msm_ioremap(pdev, "gpucc"); + if (IS_ERR(gpu->gpucc_io)) + gpu->gpucc_io = NULL; + /* Get Interrupt: */ gpu->irq = platform_get_irq(pdev, 0); if (gpu->irq < 0) { diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 4d935fe..1fe498f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -226,6 +226,7 @@ struct msm_gpu { int global_faults; void __iomem *mmio; + void __iomem *gpucc_io; int irq; struct msm_gem_address_space *aspace;