From patchwork Thu Jul 28 12:40:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Zimmermann X-Patchwork-Id: 12931248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8263FC04A68 for ; Thu, 28 Jul 2022 12:41:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 672CC18A126; Thu, 28 Jul 2022 12:41:43 +0000 (UTC) Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by gabe.freedesktop.org (Postfix) with ESMTPS id B67118BABF for ; Thu, 28 Jul 2022 12:41:06 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 5A8842035D; Thu, 28 Jul 2022 12:41:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1659012065; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FQexzAzQ69QJXehNdKzurZvb622XXrk+r9/1mnGn0p0=; b=B3lD4oX0zSOzuE3vKqupvKcGNxYzQWiQIY/SVTW0rGhmnT2dDMoUNVdAV/vOXIg0CvKqDy K33HopCVkZRSvwpGn4yH87/70djvqUYcpgGkEstl+d3UaanHakCC+oHzrElsadj1jVMloi rqmp5ailMOukGf8Dh2Xyi7Iw983r3gA= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1659012065; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FQexzAzQ69QJXehNdKzurZvb622XXrk+r9/1mnGn0p0=; b=hSqsuIT8+dWs3H/6nwZV6NwwOJbamfO1o+ysLY4niZ05R9lz1Ib3uYFRDehiSg8X/tz8eQ iYqN7IERDK+tEIBw== Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 2C2BE13A7E; Thu, 28 Jul 2022 12:41:05 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id SJ77CeGD4mJwMAAAMHmgww (envelope-from ); Thu, 28 Jul 2022 12:41:05 +0000 From: Thomas Zimmermann To: jfalempe@redhat.com, sam@ravnborg.org, airlied@redhat.com, airlied@linux.ie, daniel@ffwll.ch Subject: [PATCH v3 02/14] drm/mgag200: Move DAC-register setup into model-specific code Date: Thu, 28 Jul 2022 14:40:51 +0200 Message-Id: <20220728124103.30159-3-tzimmermann@suse.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220728124103.30159-1-tzimmermann@suse.de> References: <20220728124103.30159-1-tzimmermann@suse.de> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Zimmermann , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Provide an init function for each model's DAC registers. Remove the shared helper. The code for initializing the DAC registers consisted of a large table of default value, plus many exceptions for the various G200 models. Providing a per-model implementation makes if more readable. At some point, some of the initialization should probably move into the modesetting code. v2: * don't duplicate DAC values unnecessarily (Sam, Jocelyn) Signed-off-by: Thomas Zimmermann Reviewed-by: Jocelyn Falempe Tested-by: Jocelyn Falempe --- drivers/gpu/drm/mgag200/mgag200_drv.h | 30 +++++++++ drivers/gpu/drm/mgag200/mgag200_g200.c | 25 +++++++ drivers/gpu/drm/mgag200/mgag200_g200eh.c | 26 ++++++++ drivers/gpu/drm/mgag200/mgag200_g200eh3.c | 2 + drivers/gpu/drm/mgag200/mgag200_g200er.c | 25 +++++++ drivers/gpu/drm/mgag200/mgag200_g200ev.c | 27 ++++++++ drivers/gpu/drm/mgag200/mgag200_g200ew3.c | 2 + drivers/gpu/drm/mgag200/mgag200_g200se.c | 30 +++++++++ drivers/gpu/drm/mgag200/mgag200_g200wb.c | 24 +++++++ drivers/gpu/drm/mgag200/mgag200_mode.c | 80 +---------------------- 10 files changed, 192 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h index 301c4ab46539..face2904556a 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.h +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -123,6 +123,33 @@ #define MGA_MISC_OUT 0x1fc2 #define MGA_MISC_IN 0x1fcc +/* + * TODO: This is a pretty large set of default values for all kinds of + * settings. It should be split and set in the various DRM helpers, + * such as the CRTC reset or atomic_enable helpers. The PLL values + * probably belong to each model's PLL code. + */ +#define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp) \ + /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, \ + /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, \ + /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, \ + /* 0x18: */ (xvrefctrl), \ + /* 0x19: */ 0, \ + /* 0x1a: */ (xpixclkctrl), \ + /* 0x1b: */ 0xff, 0xbf, 0x20, \ + /* 0x1e: */ (xmiscctrl), \ + /* 0x1f: */ 0x20, \ + /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + /* 0x28: */ 0x00, 0x00, 0x00, 0x00, \ + /* 0x2c: */ (xsyspllm), \ + /* 0x2d: */ (xsysplln), \ + /* 0x2e: */ (xsyspllp), \ + /* 0x2f: */ 0x40, \ + /* 0x30: */ 0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83, \ + /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a, \ + /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, \ + /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 \ + #define MGAG200_MAX_FB_HEIGHT 4096 #define MGAG200_MAX_FB_WIDTH 4096 @@ -295,10 +322,12 @@ struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct enum mga_type type); struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv, enum mga_type type); +void mgag200_g200wb_init_registers(struct mga_device *mdev); struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv, enum mga_type type); struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv, enum mga_type type); +void mgag200_g200eh_init_registers(struct mga_device *mdev); struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const struct drm_driver *drv, enum mga_type type); struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, const struct drm_driver *drv, @@ -310,6 +339,7 @@ struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, const str /* mgag200_mode.c */ resource_size_t mgag200_device_probe_vram(struct mga_device *mdev); +void mgag200_init_registers(struct mga_device *mdev); int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_fb_available); /* mgag200_i2c.c */ diff --git a/drivers/gpu/drm/mgag200/mgag200_g200.c b/drivers/gpu/drm/mgag200/mgag200_g200.c index 674385921b7f..4a5af20efa36 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200.c @@ -30,6 +30,29 @@ static int mgag200_g200_init_pci_options(struct pci_dev *pdev) return mgag200_init_pci_options(pdev, option, 0x00008000); } +static void mgag200_g200_init_registers(struct mgag200_g200_device *g200) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x00, 0xc9, 0x1f, + 0x04, 0x2d, 0x19) + }; + + struct mga_device *mdev = &g200->base; + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); ++i) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i >= 0x30) && (i <= 0x37))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + mgag200_init_registers(mdev); +} + /* * DRM Device */ @@ -191,6 +214,8 @@ struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct if (ret) return ERR_PTR(ret); + mgag200_g200_init_registers(g200); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh.c b/drivers/gpu/drm/mgag200/mgag200_g200eh.c index 1b9a22728744..f2c53fe8d927 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200eh.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh.c @@ -6,6 +6,30 @@ #include "mgag200_drv.h" +void mgag200_g200eh_init_registers(struct mga_device *mdev) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x00, 0xc9, + MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS, + 0x00, 0x00, 0x00) + }; + + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i >= 0x30) && (i <= 0x37)) || + ((i >= 0x44) && (i <= 0x4e))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + mgag200_init_registers(mdev); +} + /* * DRM device */ @@ -40,6 +64,8 @@ struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const stru if (ret) return ERR_PTR(ret); + mgag200_g200eh_init_registers(mdev); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c index 438cda1b14c9..adb9190b62af 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c @@ -41,6 +41,8 @@ struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev, if (ret) return ERR_PTR(ret); + mgag200_g200eh_init_registers(mdev); // same as G200EH + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c b/drivers/gpu/drm/mgag200/mgag200_g200er.c index 0790d4e6463d..7bee20459ab6 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200er.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200er.c @@ -6,6 +6,29 @@ #include "mgag200_drv.h" +static void mgag200_g200er_init_registers(struct mga_device *mdev) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x00, 0xc9, 0x1f, 0x00, 0x00, 0x00) + }; + + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i >= 0x30) && (i <= 0x37))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + WREG_DAC(0x90, 0); /* G200ER specific */ + + mgag200_init_registers(mdev); +} + /* * DRM device */ @@ -36,6 +59,8 @@ struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, const stru if (ret) return ERR_PTR(ret); + mgag200_g200er_init_registers(mdev); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c b/drivers/gpu/drm/mgag200/mgag200_g200ev.c index 5353422d0eef..0dc5c342e7c4 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200ev.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200ev.c @@ -6,6 +6,31 @@ #include "mgag200_drv.h" +static void mgag200_g200ev_init_registers(struct mga_device *mdev) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x00, + MGA1064_PIX_CLK_CTL_SEL_PLL, + MGA1064_MISC_CTL_VGA8 | MGA1064_MISC_CTL_DAC_RAM_CS, + 0x00, 0x00, 0x00) + }; + + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i >= 0x30) && (i <= 0x37)) || + ((i >= 0x44) && (i <= 0x4e))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + mgag200_init_registers(mdev); +} + /* * DRM device */ @@ -40,6 +65,8 @@ struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const stru if (ret) return ERR_PTR(ret); + mgag200_g200ev_init_registers(mdev); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c index 3bfc1324cf78..d86284c0eb4d 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c @@ -50,6 +50,8 @@ struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev, if (ret) return ERR_PTR(ret); + mgag200_g200wb_init_registers(mdev); // same as G200WB + vram_available = mgag200_g200ew3_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c index 0a3e66695e22..bd8fc7a177c2 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c @@ -28,6 +28,34 @@ static int mgag200_g200se_init_pci_options(struct pci_dev *pdev) return mgag200_init_pci_options(pdev, option, 0x00008000); } +static void mgag200_g200se_init_registers(struct mgag200_g200se_device *g200se) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x03, + MGA1064_PIX_CLK_CTL_SEL_PLL, + MGA1064_MISC_CTL_DAC_EN | + MGA1064_MISC_CTL_VGA8 | + MGA1064_MISC_CTL_DAC_RAM_CS, + 0x00, 0x00, 0x00) + }; + + struct mga_device *mdev = &g200se->base; + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)) || + ((i >= 0x30) && (i <= 0x37))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + mgag200_init_registers(mdev); +} + /* * DRM device */ @@ -120,6 +148,8 @@ struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const stru if (ret) return ERR_PTR(ret); + mgag200_g200se_init_registers(g200se); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_g200wb.c b/drivers/gpu/drm/mgag200/mgag200_g200wb.c index c8450ac8eaec..05f17986b95a 100644 --- a/drivers/gpu/drm/mgag200/mgag200_g200wb.c +++ b/drivers/gpu/drm/mgag200/mgag200_g200wb.c @@ -6,6 +6,28 @@ #include "mgag200_drv.h" +void mgag200_g200wb_init_registers(struct mga_device *mdev) +{ + static const u8 dacvalue[] = { + MGAG200_DAC_DEFAULT(0x07, 0xc9, 0x1f, 0x00, 0x00, 0x00) + }; + + size_t i; + + for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { + if ((i <= 0x17) || + (i == 0x1b) || + (i == 0x1c) || + ((i >= 0x1f) && (i <= 0x29)) || + ((i >= 0x30) && (i <= 0x37)) || + ((i >= 0x44) && (i <= 0x4e))) + continue; + WREG_DAC(i, dacvalue[i]); + } + + mgag200_init_registers(mdev); +} + /* * DRM device */ @@ -40,6 +62,8 @@ struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const stru if (ret) return ERR_PTR(ret); + mgag200_g200wb_init_registers(mdev); + vram_available = mgag200_device_probe_vram(mdev); ret = mgag200_modeset_init(mdev, vram_available); diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index 78fdb3148ed7..ba5661cc6686 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -266,86 +266,10 @@ static void mgag200_set_startadd(struct mga_device *mdev, WREG_ECRT(0x00, crtcext0); } -static void mgag200_set_dac_regs(struct mga_device *mdev) -{ - size_t i; - u8 dacvalue[] = { - /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, - /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, - /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, - /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, - /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, - /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, - /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, - /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, - /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 - }; - - switch (mdev->type) { - case G200_PCI: - case G200_AGP: - dacvalue[MGA1064_SYS_PLL_M] = 0x04; - dacvalue[MGA1064_SYS_PLL_N] = 0x2D; - dacvalue[MGA1064_SYS_PLL_P] = 0x19; - break; - case G200_SE_A: - case G200_SE_B: - dacvalue[MGA1064_VREF_CTL] = 0x03; - dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; - dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | - MGA1064_MISC_CTL_VGA8 | - MGA1064_MISC_CTL_DAC_RAM_CS; - break; - case G200_WB: - case G200_EW3: - dacvalue[MGA1064_VREF_CTL] = 0x07; - break; - case G200_EV: - dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; - dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | - MGA1064_MISC_CTL_DAC_RAM_CS; - break; - case G200_EH: - case G200_EH3: - dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | - MGA1064_MISC_CTL_DAC_RAM_CS; - break; - case G200_ER: - break; - } - - for (i = 0; i < ARRAY_SIZE(dacvalue); i++) { - if ((i <= 0x17) || - (i == 0x1b) || - (i == 0x1c) || - ((i >= 0x1f) && (i <= 0x29)) || - ((i >= 0x30) && (i <= 0x37))) - continue; - if (IS_G200_SE(mdev) && - ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) - continue; - if ((mdev->type == G200_EV || - mdev->type == G200_WB || - mdev->type == G200_EH || - mdev->type == G200_EW3 || - mdev->type == G200_EH3) && - (i >= 0x44) && (i <= 0x4e)) - continue; - - WREG_DAC(i, dacvalue[i]); - } - - if (mdev->type == G200_ER) - WREG_DAC(0x90, 0); -} - -static void mgag200_init_regs(struct mga_device *mdev) +void mgag200_init_registers(struct mga_device *mdev) { u8 crtc11, misc; - mgag200_set_dac_regs(mdev); - WREG_SEQ(2, 0x0f); WREG_SEQ(3, 0x00); WREG_SEQ(4, 0x0e); @@ -1126,8 +1050,6 @@ int mgag200_modeset_init(struct mga_device *mdev, resource_size_t vram_available struct drm_device *dev = &mdev->base; int ret; - mgag200_init_regs(mdev); - ret = mgag200_mode_config_init(mdev, vram_available); if (ret) return ret;