diff mbox series

[2/2] drm/panel: simple: Add EDT ETML1010G0DKA panel

Message ID 20220818124518.42080-2-d.haller@phytec.de (mailing list archive)
State New, archived
Headers show
Series [1/2] dt-bindings: display: simple: Add EDT ETML1010G0DKA panel | expand

Commit Message

Dominik Haller Aug. 18, 2022, 12:45 p.m. UTC
Add support for the EDT ETML1010G0DKA 10.1" 1280x800 LVDS panel.

Signed-off-by: Dominik Haller <d.haller@phytec.de>
---
 drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Dominik Haller Feb. 6, 2023, 2:20 p.m. UTC | #1
Hello,

ping here, this one got forgotten.
It still applies on drm-misc-next and v6.2-rc7


On 18.08.22 14:45, Dominik Haller wrote:
> Add support for the EDT ETML1010G0DKA 10.1" 1280x800 LVDS panel.
>
> Signed-off-by: Dominik Haller <d.haller@phytec.de>
> ---
>   drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index f9e1f85daef7..9314db24ab51 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1779,6 +1779,32 @@ static const struct panel_desc edt_etml0700y5dha = {
>   	.connector_type = DRM_MODE_CONNECTOR_LVDS,
>   };
>   
> +static const struct drm_display_mode edt_etml1010g0dka_mode = {
> +	.clock = 70000,
> +	.hdisplay = 1280,
> +	.hsync_start = 1280 + 100,
> +	.hsync_end = 1280 + 100 + 19,
> +	.htotal = 1280 + 100 + 19 + 41,
> +	.vdisplay = 800,
> +	.vsync_start = 800 + 4,
> +	.vsync_end = 800 + 4 + 4,
> +	.vtotal = 800 + 4 + 4 + 15,
> +	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
> +};
> +
> +static const struct panel_desc edt_etml1010g0dka = {
> +	.modes = &edt_etml1010g0dka_mode,
> +	.num_modes = 1,
> +	.bpc = 8,
> +	.size = {
> +		.width = 216,
> +		.height = 135,
> +	},
> +	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
> +	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
> +	.connector_type = DRM_MODE_CONNECTOR_LVDS,
> +};
> +
>   static const struct drm_display_mode edt_etmv570g2dhu_mode = {
>   	.clock = 25175,
>   	.hdisplay = 640,
> @@ -4057,6 +4083,9 @@ static const struct of_device_id platform_of_match[] = {
>   	}, {
>   		.compatible = "edt,etml0700y5dha",
>   		.data = &edt_etml0700y5dha,
> +	}, {
> +		.compatible = "edt,etml1010g0dka",
> +		.data = &edt_etml1010g0dka,
>   	}, {
>   		.compatible = "edt,etmv570g2dhu",
>   		.data = &edt_etmv570g2dhu,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index f9e1f85daef7..9314db24ab51 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1779,6 +1779,32 @@  static const struct panel_desc edt_etml0700y5dha = {
 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
 };
 
+static const struct drm_display_mode edt_etml1010g0dka_mode = {
+	.clock = 70000,
+	.hdisplay = 1280,
+	.hsync_start = 1280 + 100,
+	.hsync_end = 1280 + 100 + 19,
+	.htotal = 1280 + 100 + 19 + 41,
+	.vdisplay = 800,
+	.vsync_start = 800 + 4,
+	.vsync_end = 800 + 4 + 4,
+	.vtotal = 800 + 4 + 4 + 15,
+	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
+};
+
+static const struct panel_desc edt_etml1010g0dka = {
+	.modes = &edt_etml1010g0dka_mode,
+	.num_modes = 1,
+	.bpc = 8,
+	.size = {
+		.width = 216,
+		.height = 135,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
+	.connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
 	.clock = 25175,
 	.hdisplay = 640,
@@ -4057,6 +4083,9 @@  static const struct of_device_id platform_of_match[] = {
 	}, {
 		.compatible = "edt,etml0700y5dha",
 		.data = &edt_etml0700y5dha,
+	}, {
+		.compatible = "edt,etml1010g0dka",
+		.data = &edt_etml1010g0dka,
 	}, {
 		.compatible = "edt,etmv570g2dhu",
 		.data = &edt_etmv570g2dhu,