From patchwork Mon Aug 29 09:58:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 12957623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5922CECAAD4 for ; Mon, 29 Aug 2022 09:58:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 954D810F152; Mon, 29 Aug 2022 09:58:13 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0D4D510F13C; Mon, 29 Aug 2022 09:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661767069; x=1693303069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=04l72mGa5RZDA9Jfx1Flib/jQulzbYfdi65CrNhdyTg=; b=lv/JzUju89HncUATDF8mZeqQA7M2W0Zip2wLACT+a4PabGtjNe5axY6n TE+hxth9wFoD9n+UI/LF/pjRa1b+WW0x//0TGhwdI9IQ/wE5YhP04One9 bN6BQVfRR+Qoffbvh6RIUnhnD8Jfzv21qaMRUnxSYcnMe3Cs0rJuJkAV5 sKQBlw+5AoqywZNh3b7l7wmD4QmG7LhFlgtQzvu5+VVhnv6gGnGa/kxQv o5wjhi6UyxZa3thKlpSdGRV1IyC2Cd/KuYCu6cHW9rLyuN+ISesRsJJML 8EMwJWaW3jvMAsRA9fU+jsc6yzOhR6Qu0BuaBe2IYd7YUkiMkVEyi3CGI A==; X-IronPort-AV: E=McAfee;i="6500,9779,10453"; a="293601517" X-IronPort-AV: E=Sophos;i="5.93,272,1654585200"; d="scan'208";a="293601517" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2022 02:57:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,272,1654585200"; d="scan'208";a="700527739" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by FMSMGA003.fm.intel.com with ESMTP; 29 Aug 2022 02:57:46 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm: Add missing DP DSC extended capability definitions. Date: Mon, 29 Aug 2022 12:58:29 +0300 Message-Id: <20220829095832.21770-2-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.24.1.485.gad05a3d8e5 In-Reply-To: <20220829095832.21770-1-stanislav.lisovskiy@intel.com> References: <20220829095832.21770-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: manasi.d.navare@intel.com, vinod.govindapillai@intel.com, jani.nikula@intel.com, dri-devel@lists.freedesktop.org, Stanislav.Lisovskiy@intel.com, jani.saarinen@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Reviewed-by: Vinod Govindapillai Signed-off-by: Stanislav Lisovskiy --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1