From patchwork Sun Sep 11 15:37:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 12972933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32F38C54EE9 for ; Sun, 11 Sep 2022 15:38:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D34AA10E4C9; Sun, 11 Sep 2022 15:38:25 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 31A5610E4C7 for ; Sun, 11 Sep 2022 15:37:51 +0000 (UTC) X-UUID: c073cd5cf4f44b48aa92b6529d32f86f-20220911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ul9i8erPB1DoaRLOoK8QSUHMoEYMlUQuYgsmBM/7Fug=; b=UkYXEwhB973pRL3TE9kFOeHSuKyCrWtvlq5oJ9jS/2tm+AYPMRJHcKwOuOgH45TY2mZBjYm4f9yapYJ7+lLiMBoWDSb6zPM+5JKl0k3ze1TuI5+Q8CgPWTtT+r0sluNI8E26Efgj8DaDnKs4CMF50YdiVI3dY51DsN1DyosllSk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10, REQID:dd566a3f-c20a-4c0d-acae-01685e0d55fb, OB:0, L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Relea se_Ham,ACTION:release,TS:100 X-CID-INFO: VERSION:1.1.10, REQID:dd566a3f-c20a-4c0d-acae-01685e0d55fb, OB:0, LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS 981B3D,ACTION:quarantine,TS:100 X-CID-META: VersionHash:84eae18, CLOUDID:2366fef5-6e85-48d9-afd8-0504bbfe04cb, C OID:be9d65baf543,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c073cd5cf4f44b48aa92b6529d32f86f-20220911 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 455663802; Sun, 11 Sep 2022 23:37:45 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sun, 11 Sep 2022 23:37:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sun, 11 Sep 2022 23:37:44 +0800 From: Jason-JH.Lin To: Chun-Kuang Hu , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Subject: [PATCH v3 8/9] drm/mediatek: Add clear RELAY_MODE bit to set gamma Date: Sun, 11 Sep 2022 23:37:33 +0800 Message-ID: <20220911153734.24243-9-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220911153734.24243-1-jason-jh.lin@mediatek.com> References: <20220911153734.24243-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "Jason-JH.Lin" , Singo Chang , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Rex-BC Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the bootlaoder may set the RELAY_MODE to gamma be for the kerenl, we have to clear the RELAY_MODE bit to make sure that the gamma is enabled correctly. Fixes: b10023b03082 ("FROMGIT: drm/mediatek: Separate gamma module") Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 4e67f1503b9a..77cc344b9c02 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -18,6 +18,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -99,6 +100,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); + reg = reg & ~RELAY_MODE; reg = reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT;