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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id q17-20020adff951000000b00228dff8d975sm2098257wrr.109.2022.09.15.03.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 03:29:29 -0700 (PDT) From: Robert Foss To: andrzej.hajda@intel.com, narmstrong@baylibre.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie, daniel@ffwll.ch, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Chris Morgan , devicetree@vger.kernel.org Subject: [PATCH v1 2/2] Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting" Date: Thu, 15 Sep 2022 12:29:24 +0200 Message-Id: <20220915102924.370090-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220915102924.370090-1-robert.foss@linaro.org> References: <20220915102924.370090-1-robert.foss@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Revert this patch since it depends on devicetree functionality that previously has been reverted in the below commit. commit e798ba3374a1 ("Revert "dt-bindings: Add byteswap order to chrontel ch7033"") This reverts commit ce9564cfc9aea65e68eb343c599317633bc2321a. Signed-off-by: Robert Foss --- drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c index c5719908ce2d..ba060277c3fd 100644 --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c @@ -68,7 +68,6 @@ enum { BYTE_SWAP_GBR = 3, BYTE_SWAP_BRG = 4, BYTE_SWAP_BGR = 5, - BYTE_SWAP_MAX = 6, }; /* Page 0, Register 0x19 */ @@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, int hsynclen = mode->hsync_end - mode->hsync_start; int vbporch = mode->vsync_start - mode->vdisplay; int vsynclen = mode->vsync_end - mode->vsync_start; - u8 byte_swap; - int ret; /* * Page 4 @@ -401,16 +398,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge, regmap_write(priv->regmap, 0x15, vbporch); regmap_write(priv->regmap, 0x16, vsynclen); - /* Input color swap. Byte order is optional and will default to - * BYTE_SWAP_BGR to preserve backwards compatibility with existing - * driver. - */ - ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap", - &byte_swap); - if (!ret && byte_swap < BYTE_SWAP_MAX) - regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap); - else - regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); + /* Input color swap. */ + regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); /* Input clock and sync polarity. */ regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);