diff mbox series

drm/rockchip: vop2: Register Esmart0-win0 as primary plane

Message ID 20220926081643.304759-1-s.hauer@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series drm/rockchip: vop2: Register Esmart0-win0 as primary plane | expand

Commit Message

Sascha Hauer Sept. 26, 2022, 8:16 a.m. UTC
Esmart0-win0 could serve as primary plane, so mark it as such. On
RK3568 this window will never be used as primary plane, because the
three windows at the beginning of the rk3568_vop_win_data[] array
will be used. On RK3566 however, two of the windows at the beginning
of the rk3568_vop_win_data[] array cannot not be used due to hardware
limitations, so without this patch we end up with CRTCs without primary
planes when multiple VPs are active.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Chris Morgan Sept. 26, 2022, 12:58 p.m. UTC | #1
On Mon, Sep 26, 2022 at 10:16:43AM +0200, Sascha Hauer wrote:
> Esmart0-win0 could serve as primary plane, so mark it as such. On
> RK3568 this window will never be used as primary plane, because the
> three windows at the beginning of the rk3568_vop_win_data[] array
> will be used. On RK3566 however, two of the windows at the beginning
> of the rk3568_vop_win_data[] array cannot not be used due to hardware
> limitations, so without this patch we end up with CRTCs without primary
> planes when multiple VPs are active.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

I have been testing this for a few days and it works well for me on 2
distinct rk3566 based devices (Anbernic RG353P and Anbernic RG503).

Tested-by: Chris Morgan <macromorgan@hotmail.com>

> ---
>  drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> index 9bf0637bf8e26..9d30aa73b5422 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> @@ -188,7 +188,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
>  		.base = 0x1800,
>  		.layer_sel_id = 2,
>  		.supported_rotations = DRM_MODE_REFLECT_Y,
> -		.type = DRM_PLANE_TYPE_OVERLAY,
> +		.type = DRM_PLANE_TYPE_PRIMARY,
>  		.max_upscale_factor = 8,
>  		.max_downscale_factor = 8,
>  		.dly = { 20, 47, 41 },
> -- 
> 2.30.2
>
Heiko Stübner Oct. 29, 2022, 10:08 p.m. UTC | #2
On Mon, 26 Sep 2022 10:16:43 +0200, Sascha Hauer wrote:
> Esmart0-win0 could serve as primary plane, so mark it as such. On
> RK3568 this window will never be used as primary plane, because the
> three windows at the beginning of the rk3568_vop_win_data[] array
> will be used. On RK3566 however, two of the windows at the beginning
> of the rk3568_vop_win_data[] array cannot not be used due to hardware
> limitations, so without this patch we end up with CRTCs without primary
> planes when multiple VPs are active.
> 
> [...]

Applied, thanks!

[1/1] drm/rockchip: vop2: Register Esmart0-win0 as primary plane
      commit: de4a4c8f64021b02aaa8ab21a82fe1f11a17b975

Best regards,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
index 9bf0637bf8e26..9d30aa73b5422 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -188,7 +188,7 @@  static const struct vop2_win_data rk3568_vop_win_data[] = {
 		.base = 0x1800,
 		.layer_sel_id = 2,
 		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_OVERLAY,
+		.type = DRM_PLANE_TYPE_PRIMARY,
 		.max_upscale_factor = 8,
 		.max_downscale_factor = 8,
 		.dly = { 20, 47, 41 },