From patchwork Thu Sep 29 01:44:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: allen X-Patchwork-Id: 12993360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45406C32771 for ; Thu, 29 Sep 2022 01:47:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82B4E10E922; Thu, 29 Sep 2022 01:47:42 +0000 (UTC) Received: from ironport.ite.com.tw (60-251-196-230.hinet-ip.hinet.net [60.251.196.230]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F8CC10E90C for ; Thu, 29 Sep 2022 01:46:06 +0000 (UTC) Received: from unknown (HELO mse.ite.com.tw) ([192.168.35.30]) by ironport.ite.com.tw with ESMTP; 29 Sep 2022 09:46:06 +0800 Received: from CSBMAIL1.internal.ite.com.tw (CSBMAIL1.internal.ite.com.tw [192.168.65.58]) by mse.ite.com.tw with ESMTP id 28T1k3xf041765; Thu, 29 Sep 2022 09:46:03 +0800 (GMT-8) (envelope-from allen.chen@ite.com.tw) Received: from VirtualBox.internal.ite.com.tw (192.168.70.46) by CSBMAIL1.internal.ite.com.tw (192.168.65.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.14; Thu, 29 Sep 2022 09:45:14 +0800 From: allen To: Subject: [PATCH v2 2/2] drm/bridge: add it6505 driver to read data-lanes and max-pixel-clock-khz from dt Date: Thu, 29 Sep 2022 09:44:52 +0800 Message-ID: <20220929014456.30077-3-allen.chen@ite.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220929014456.30077-1-allen.chen@ite.com.tw> References: <20220929014456.30077-1-allen.chen@ite.com.tw> MIME-Version: 1.0 X-Originating-IP: [192.168.70.46] X-ClientProxiedBy: CSBMAIL1.internal.ite.com.tw (192.168.65.58) To CSBMAIL1.internal.ite.com.tw (192.168.65.58) X-TM-SNTS-SMTP: F89ADB4C5CCEB304D0D91482FF0A8ED263135192E8A47F867635897E00136C642002:8 X-MAIL: mse.ite.com.tw 28T1k3xf041765 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kenneth Hung , Jernej Skrabec , Jau-Chih Tseng , David Airlie , Allen Chen , "open list:DRM DRIVERS" , Neil Armstrong , open list , Robert Foss , Pin-yen Lin , Hermes Wu , Laurent Pinchart , Andrzej Hajda , Jonas Karlman Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: allen chen Add driver to read data-lanes and max-pixel-clock-khz from dt property to restrict output bandwidth. Signed-off-by: Allen chen Signed-off-by: Pin-yen Lin --- drivers/gpu/drm/bridge/ite-it6505.c | 35 ++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index 2767b70fa2cb..cfa25a176a29 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -436,6 +436,8 @@ struct it6505 { bool powered; bool hpd_state; u32 afe_setting; + u32 max_dpi_pixel_clock; + u32 max_lane_count; enum hdcp_state hdcp_status; struct delayed_work hdcp_work; struct work_struct hdcp_wait_ksv_list; @@ -1475,7 +1477,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505) it6505->lane_count = link->num_lanes; DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", it6505->lane_count); - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); + it6505->lane_count = min_t(int, it6505->lane_count, + it6505->max_lane_count); it6505->branch_device = drm_dp_is_branch(it6505->dpcd); DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", @@ -2901,7 +2904,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_INTERLACE) return MODE_NO_INTERLACE; - if (mode->clock > DPI_PIXEL_CLK_MAX) + if (mode->clock > it6505->max_dpi_pixel_clock) return MODE_CLOCK_HIGH; it6505->video_info.clock = mode->clock; @@ -3066,6 +3069,8 @@ static void it6505_parse_dt(struct it6505 *it6505) { struct device *dev = &it6505->client->dev; u32 *afe_setting = &it6505->afe_setting; + u32 *max_lane_count = &it6505->max_lane_count; + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock; it6505->lane_swap_disabled = device_property_read_bool(dev, "no-laneswap"); @@ -3081,7 +3086,31 @@ static void it6505_parse_dt(struct it6505 *it6505) } else { *afe_setting = 0; } - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); + + if (device_property_read_u32(dev, "data-lanes", + max_lane_count) == 0) { + if (*max_lane_count > 4 || *max_lane_count == 3) { + dev_err(dev, "max lane count error, use default"); + *max_lane_count = MAX_LANE_COUNT; + } + } else { + *max_lane_count = MAX_LANE_COUNT; + } + + if (device_property_read_u32(dev, "max-pixel-clock-khz", + max_dpi_pixel_clock) == 0) { + if (*max_dpi_pixel_clock > 297000) { + dev_err(dev, "max pixel clock error, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + } else { + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", + it6505->afe_setting, it6505->max_lane_count); + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", + it6505->max_dpi_pixel_clock); } static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,