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Tue, 4 Oct 2022 21:15:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT115.mail.protection.outlook.com (10.13.177.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5709.10 via Frontend Transport; Tue, 4 Oct 2022 21:15:51 +0000 Received: from dev.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 4 Oct 2022 16:15:50 -0500 From: Alex Hung To: , Subject: [RFC PATCH 4/5] drm/amd/display: Enable plane 3DLUT mode Date: Tue, 4 Oct 2022 15:14:50 -0600 Message-ID: <20221004211451.1475215-5-alex.hung@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004211451.1475215-1-alex.hung@amd.com> References: <20221004211451.1475215-1-alex.hung@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT115:EE_|CH0PR12MB5187:EE_ X-MS-Office365-Filtering-Correlation-Id: 59495d62-4951-4384-b1cd-08daa64d9de3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199015)(40470700004)(36840700001)(46966006)(4326008)(110136005)(70586007)(70206006)(478600001)(41300700001)(8936002)(316002)(54906003)(36756003)(36860700001)(40480700001)(356005)(40460700003)(82740400003)(82310400005)(7696005)(1076003)(2616005)(26005)(426003)(16526019)(186003)(47076005)(86362001)(81166007)(336012)(44832011)(2906002)(8676002)(5660300002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 21:15:51.7359 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59495d62-4951-4384-b1cd-08daa64d9de3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5187 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mwen@igalia.com, bhawanpreet.lakha@amd.com, Alex Hung Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable the 3D LUT mode supported by amdgpu. Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this proposal is sent to IGT mailing list. Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++ drivers/gpu/drm/drm_color_mgmt.c | 31 +++++++++++++++++++ include/drm/drm_plane.h | 2 ++ 3 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ee277f357140..7094578a683f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8008,6 +8008,9 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, /* TODO need to check ASICs */ drm_plane_create_3d_lut_properties(plane->dev, plane, 1); + res = drm_plane_color_add_3dlut_mode(plane, "3dlut_17_12bit", &lut_3d_mode_17_12bit, sizeof(lut_3d_mode_17_12bit)); + if (res) + return res; drm_plane_attach_3dlut_properties(plane); /* Create (reset) the plane state */ diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 4bfe5b5c9670..5418ca24db73 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -743,6 +743,37 @@ void drm_plane_attach_3dlut_properties(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_3dlut_properties); +int drm_plane_color_add_3dlut_mode(struct drm_plane *plane, + const char *name, + const struct drm_mode_3dlut_mode *mode_3dlut, + size_t length) +{ + struct drm_property_blob *blob; + struct drm_property *prop = NULL; + int ret; + + prop = plane->lut_3d_mode_property; + + if (!prop) + return -EINVAL; + + if (length == 0 && name) + return drm_property_add_enum(prop, 0, name); + + blob = drm_property_create_blob(plane->dev, length, mode_3dlut); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + ret = drm_property_add_enum(prop, blob->base.id, name); + if (ret) { + drm_property_blob_put(blob); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_plane_color_add_3dlut_mode); + int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 4e272144170f..f94f91466675 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -946,6 +946,8 @@ int drm_plane_create_3d_lut_properties(struct drm_device *dev, struct drm_plane *plane, int num_values); void drm_plane_attach_3dlut_properties(struct drm_plane *plane); +int drm_plane_color_add_3dlut_mode(struct drm_plane *plane, const char *name, + const struct drm_mode_3dlut_mode *mode_3dlut, size_t length); int drm_plane_color_add_gamma_degamma_mode_range(struct drm_plane *plane, const char *name, const struct drm_color_lut_range *ranges,