| Message ID | 20221004222903.23898-3-vinay.belgaumkar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/slpc: Update frequency debugfs for SLPC | expand |
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Vinay-Belgaumkar/drm-i915-slpc-Update-frequency-debugfs-for-SLPC/20221005-063101
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-rhel-8.3-func
compiler: gcc-11 (Debian 11.3.0-5) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/52d4cf9a124b92a8c435dc05307cbaa5edbffacf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Vinay-Belgaumkar/drm-i915-slpc-Update-frequency-debugfs-for-SLPC/20221005-063101
git checkout 52d4cf9a124b92a8c435dc05307cbaa5edbffacf
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/intel_rps.c:2222:6: warning: no previous prototype for 'rps_frequency_dump' [-Wmissing-prototypes]
2222 | void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
| ^~~~~~~~~~~~~~~~~~
vim +/rps_frequency_dump +2222 drivers/gpu/drm/i915/gt/intel_rps.c
2221
> 2222 void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
2223 {
2224 struct intel_gt *gt = rps_to_gt(rps);
2225 struct drm_i915_private *i915 = gt->i915;
2226 struct intel_uncore *uncore = gt->uncore;
2227 struct intel_rps_freq_caps caps;
2228 u32 rp_state_limits;
2229 u32 gt_perf_status;
2230 u32 rpmodectl, rpinclimit, rpdeclimit;
2231 u32 rpstat, cagf, reqf;
2232 u32 rpcurupei, rpcurup, rpprevup;
2233 u32 rpcurdownei, rpcurdown, rpprevdown;
2234 u32 rpupei, rpupt, rpdownei, rpdownt;
2235 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
2236
2237 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
2238 gen6_rps_get_freq_caps(rps, &caps);
2239 if (IS_GEN9_LP(i915))
2240 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
2241 else
2242 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
2243
2244 /* RPSTAT1 is in the GT power well */
2245 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2246
2247 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
2248 if (GRAPHICS_VER(i915) >= 9) {
2249 reqf >>= 23;
2250 } else {
2251 reqf &= ~GEN6_TURBO_DISABLE;
2252 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
2253 reqf >>= 24;
2254 else
2255 reqf >>= 25;
2256 }
2257 reqf = intel_gpu_freq(rps, reqf);
2258
2259 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
2260 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2261 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2262
2263 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
2264 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
2265 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
2266 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
2267 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
2268 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
2269 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
2270
2271 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
2272 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2273
2274 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
2275 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2276
2277 cagf = intel_rps_read_actual_frequency(rps);
2278
2279 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2280
2281 if (GRAPHICS_VER(i915) >= 11) {
2282 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
2283 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
2284 /*
2285 * The equivalent to the PM ISR & IIR cannot be read
2286 * without affecting the current state of the system
2287 */
2288 pm_isr = 0;
2289 pm_iir = 0;
2290 } else if (GRAPHICS_VER(i915) >= 8) {
2291 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
2292 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
2293 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
2294 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
2295 } else {
2296 pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
2297 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
2298 pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
2299 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
2300 }
2301 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
2302
2303 drm_printf(p, "Video Turbo Mode: %s\n",
2304 str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
2305 drm_printf(p, "HW control enabled: %s\n",
2306 str_yes_no(rpmodectl & GEN6_RP_ENABLE));
2307 drm_printf(p, "SW control enabled: %s\n",
2308 str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
2309
2310 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
2311 pm_ier, pm_imr, pm_mask);
2312 if (GRAPHICS_VER(i915) <= 10)
2313 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
2314 pm_isr, pm_iir);
2315 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
2316 rps->pm_intrmsk_mbz);
2317 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
2318 drm_printf(p, "Render p-state ratio: %d\n",
2319 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
2320 drm_printf(p, "Render p-state VID: %d\n",
2321 gt_perf_status & 0xff);
2322 drm_printf(p, "Render p-state limit: %d\n",
2323 rp_state_limits & 0xff);
2324 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
2325 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
2326 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
2327 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
2328 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
2329 drm_printf(p, "CAGF: %dMHz\n", cagf);
2330 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
2331 rpcurupei,
2332 intel_gt_pm_interval_to_ns(gt, rpcurupei));
2333 drm_printf(p, "RP CUR UP: %d (%lldns)\n",
2334 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
2335 drm_printf(p, "RP PREV UP: %d (%lldns)\n",
2336 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
2337 drm_printf(p, "Up threshold: %d%%\n",
2338 rps->power.up_threshold);
2339 drm_printf(p, "RP UP EI: %d (%lldns)\n",
2340 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
2341 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
2342 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
2343
2344 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
2345 rpcurdownei,
2346 intel_gt_pm_interval_to_ns(gt, rpcurdownei));
2347 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
2348 rpcurdown,
2349 intel_gt_pm_interval_to_ns(gt, rpcurdown));
2350 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
2351 rpprevdown,
2352 intel_gt_pm_interval_to_ns(gt, rpprevdown));
2353 drm_printf(p, "Down threshold: %d%%\n",
2354 rps->power.down_threshold);
2355 drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
2356 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
2357 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
2358 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
2359
2360 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
2361 intel_gpu_freq(rps, caps.min_freq));
2362 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
2363 intel_gpu_freq(rps, caps.rp1_freq));
2364 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
2365 intel_gpu_freq(rps, caps.rp0_freq));
2366 drm_printf(p, "Max overclocked frequency: %dMHz\n",
2367 intel_gpu_freq(rps, rps->max_freq));
2368
2369 drm_printf(p, "Current freq: %d MHz\n",
2370 intel_gpu_freq(rps, rps->cur_freq));
2371 drm_printf(p, "Actual freq: %d MHz\n", cagf);
2372 drm_printf(p, "Idle freq: %d MHz\n",
2373 intel_gpu_freq(rps, rps->idle_freq));
2374 drm_printf(p, "Min freq: %d MHz\n",
2375 intel_gpu_freq(rps, rps->min_freq));
2376 drm_printf(p, "Boost freq: %d MHz\n",
2377 intel_gpu_freq(rps, rps->boost_freq));
2378 drm_printf(p, "Max freq: %d MHz\n",
2379 intel_gpu_freq(rps, rps->max_freq));
2380 drm_printf(p,
2381 "efficient (RPe) frequency: %d MHz\n",
2382 intel_gpu_freq(rps, rps->efficient_freq));
2383 }
2384
Hi Vinay,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Vinay-Belgaumkar/drm-i915-slpc-Update-frequency-debugfs-for-SLPC/20221005-063101
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-allyesconfig
compiler: gcc-11 (Debian 11.3.0-5) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/52d4cf9a124b92a8c435dc05307cbaa5edbffacf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Vinay-Belgaumkar/drm-i915-slpc-Update-frequency-debugfs-for-SLPC/20221005-063101
git checkout 52d4cf9a124b92a8c435dc05307cbaa5edbffacf
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/intel_rps.c:2222:6: error: no previous prototype for 'rps_frequency_dump' [-Werror=missing-prototypes]
2222 | void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/rps_frequency_dump +2222 drivers/gpu/drm/i915/gt/intel_rps.c
2221
> 2222 void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
2223 {
2224 struct intel_gt *gt = rps_to_gt(rps);
2225 struct drm_i915_private *i915 = gt->i915;
2226 struct intel_uncore *uncore = gt->uncore;
2227 struct intel_rps_freq_caps caps;
2228 u32 rp_state_limits;
2229 u32 gt_perf_status;
2230 u32 rpmodectl, rpinclimit, rpdeclimit;
2231 u32 rpstat, cagf, reqf;
2232 u32 rpcurupei, rpcurup, rpprevup;
2233 u32 rpcurdownei, rpcurdown, rpprevdown;
2234 u32 rpupei, rpupt, rpdownei, rpdownt;
2235 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
2236
2237 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
2238 gen6_rps_get_freq_caps(rps, &caps);
2239 if (IS_GEN9_LP(i915))
2240 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
2241 else
2242 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
2243
2244 /* RPSTAT1 is in the GT power well */
2245 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2246
2247 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
2248 if (GRAPHICS_VER(i915) >= 9) {
2249 reqf >>= 23;
2250 } else {
2251 reqf &= ~GEN6_TURBO_DISABLE;
2252 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
2253 reqf >>= 24;
2254 else
2255 reqf >>= 25;
2256 }
2257 reqf = intel_gpu_freq(rps, reqf);
2258
2259 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
2260 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2261 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2262
2263 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
2264 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
2265 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
2266 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
2267 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
2268 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
2269 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
2270
2271 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
2272 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2273
2274 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
2275 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2276
2277 cagf = intel_rps_read_actual_frequency(rps);
2278
2279 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2280
2281 if (GRAPHICS_VER(i915) >= 11) {
2282 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
2283 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
2284 /*
2285 * The equivalent to the PM ISR & IIR cannot be read
2286 * without affecting the current state of the system
2287 */
2288 pm_isr = 0;
2289 pm_iir = 0;
2290 } else if (GRAPHICS_VER(i915) >= 8) {
2291 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
2292 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
2293 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
2294 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
2295 } else {
2296 pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
2297 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
2298 pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
2299 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
2300 }
2301 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
2302
2303 drm_printf(p, "Video Turbo Mode: %s\n",
2304 str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO));
2305 drm_printf(p, "HW control enabled: %s\n",
2306 str_yes_no(rpmodectl & GEN6_RP_ENABLE));
2307 drm_printf(p, "SW control enabled: %s\n",
2308 str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE));
2309
2310 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
2311 pm_ier, pm_imr, pm_mask);
2312 if (GRAPHICS_VER(i915) <= 10)
2313 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n",
2314 pm_isr, pm_iir);
2315 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
2316 rps->pm_intrmsk_mbz);
2317 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
2318 drm_printf(p, "Render p-state ratio: %d\n",
2319 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
2320 drm_printf(p, "Render p-state VID: %d\n",
2321 gt_perf_status & 0xff);
2322 drm_printf(p, "Render p-state limit: %d\n",
2323 rp_state_limits & 0xff);
2324 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat);
2325 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl);
2326 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit);
2327 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
2328 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf);
2329 drm_printf(p, "CAGF: %dMHz\n", cagf);
2330 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n",
2331 rpcurupei,
2332 intel_gt_pm_interval_to_ns(gt, rpcurupei));
2333 drm_printf(p, "RP CUR UP: %d (%lldns)\n",
2334 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
2335 drm_printf(p, "RP PREV UP: %d (%lldns)\n",
2336 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
2337 drm_printf(p, "Up threshold: %d%%\n",
2338 rps->power.up_threshold);
2339 drm_printf(p, "RP UP EI: %d (%lldns)\n",
2340 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
2341 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n",
2342 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
2343
2344 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n",
2345 rpcurdownei,
2346 intel_gt_pm_interval_to_ns(gt, rpcurdownei));
2347 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n",
2348 rpcurdown,
2349 intel_gt_pm_interval_to_ns(gt, rpcurdown));
2350 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n",
2351 rpprevdown,
2352 intel_gt_pm_interval_to_ns(gt, rpprevdown));
2353 drm_printf(p, "Down threshold: %d%%\n",
2354 rps->power.down_threshold);
2355 drm_printf(p, "RP DOWN EI: %d (%lldns)\n",
2356 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
2357 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n",
2358 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
2359
2360 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
2361 intel_gpu_freq(rps, caps.min_freq));
2362 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n",
2363 intel_gpu_freq(rps, caps.rp1_freq));
2364 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n",
2365 intel_gpu_freq(rps, caps.rp0_freq));
2366 drm_printf(p, "Max overclocked frequency: %dMHz\n",
2367 intel_gpu_freq(rps, rps->max_freq));
2368
2369 drm_printf(p, "Current freq: %d MHz\n",
2370 intel_gpu_freq(rps, rps->cur_freq));
2371 drm_printf(p, "Actual freq: %d MHz\n", cagf);
2372 drm_printf(p, "Idle freq: %d MHz\n",
2373 intel_gpu_freq(rps, rps->idle_freq));
2374 drm_printf(p, "Min freq: %d MHz\n",
2375 intel_gpu_freq(rps, rps->min_freq));
2376 drm_printf(p, "Boost freq: %d MHz\n",
2377 intel_gpu_freq(rps, rps->boost_freq));
2378 drm_printf(p, "Max freq: %d MHz\n",
2379 intel_gpu_freq(rps, rps->max_freq));
2380 drm_printf(p,
2381 "efficient (RPe) frequency: %d MHz\n",
2382 intel_gpu_freq(rps, rps->efficient_freq));
2383 }
2384
On Tue, 04 Oct 2022, Vinay Belgaumkar <vinay.belgaumkar@intel.com> wrote: > Read the values stored in the SLPC structures. Remove the > fields that are no longer valid (like RPS interrupts) as > well. > > v2: Move all functionality changes to this patch (Jani) > > Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rps.c | 46 ++++++++++++++++++++++++++++- > 1 file changed, 45 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 737db780db00..8181d85e89f8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2219,7 +2219,7 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) > return intel_gpu_freq(rps, rps->min_freq); > } > > -void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > +void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > { > struct intel_gt *gt = rps_to_gt(rps); > struct drm_i915_private *i915 = gt->i915; > @@ -2382,6 +2382,50 @@ void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > intel_gpu_freq(rps, rps->efficient_freq)); > } > > +static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > +{ > + struct intel_gt *gt = rps_to_gt(rps); > + struct intel_uncore *uncore = gt->uncore; > + struct intel_rps_freq_caps caps; > + u32 pm_mask; > + > + gen6_rps_get_freq_caps(rps, &caps); > + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); > + > + drm_printf(p, "PM MASK=0x%08x\n", pm_mask); > + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > + rps->pm_intrmsk_mbz); > + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); > + drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); > + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > + intel_gpu_freq(rps, caps.min_freq)); > + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", > + intel_gpu_freq(rps, caps.rp1_freq)); > + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", > + intel_gpu_freq(rps, caps.rp0_freq)); > + drm_printf(p, "Current freq: %d MHz\n", > + intel_rps_get_requested_frequency(rps)); > + drm_printf(p, "Actual freq: %d MHz\n", > + intel_rps_read_actual_frequency(rps)); > + drm_printf(p, "Min freq: %d MHz\n", > + intel_rps_get_min_frequency(rps)); > + drm_printf(p, "Boost freq: %d MHz\n", > + intel_rps_get_boost_frequency(rps)); > + drm_printf(p, "Max freq: %d MHz\n", > + intel_rps_get_max_frequency(rps)); > + drm_printf(p, > + "efficient (RPe) frequency: %d MHz\n", > + intel_gpu_freq(rps, caps.rp1_freq)); > +} > + > +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > +{ > + if (!rps_uses_slpc(rps)) Please don't use "if not" when you have two branches like this. Just flip them around and use the positive. BR, Jani. > + return rps_frequency_dump(rps, p); > + else > + return slpc_frequency_dump(rps, p); > +} > + > static int set_max_freq(struct intel_rps *rps, u32 val) > { > struct drm_i915_private *i915 = rps_to_i915(rps);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 737db780db00..8181d85e89f8 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2219,7 +2219,7 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) return intel_gpu_freq(rps, rps->min_freq); } -void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) +void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) { struct intel_gt *gt = rps_to_gt(rps); struct drm_i915_private *i915 = gt->i915; @@ -2382,6 +2382,50 @@ void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) intel_gpu_freq(rps, rps->efficient_freq)); } +static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) +{ + struct intel_gt *gt = rps_to_gt(rps); + struct intel_uncore *uncore = gt->uncore; + struct intel_rps_freq_caps caps; + u32 pm_mask; + + gen6_rps_get_freq_caps(rps, &caps); + pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); + + drm_printf(p, "PM MASK=0x%08x\n", pm_mask); + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", + rps->pm_intrmsk_mbz); + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); + drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", + intel_gpu_freq(rps, caps.min_freq)); + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", + intel_gpu_freq(rps, caps.rp1_freq)); + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", + intel_gpu_freq(rps, caps.rp0_freq)); + drm_printf(p, "Current freq: %d MHz\n", + intel_rps_get_requested_frequency(rps)); + drm_printf(p, "Actual freq: %d MHz\n", + intel_rps_read_actual_frequency(rps)); + drm_printf(p, "Min freq: %d MHz\n", + intel_rps_get_min_frequency(rps)); + drm_printf(p, "Boost freq: %d MHz\n", + intel_rps_get_boost_frequency(rps)); + drm_printf(p, "Max freq: %d MHz\n", + intel_rps_get_max_frequency(rps)); + drm_printf(p, + "efficient (RPe) frequency: %d MHz\n", + intel_gpu_freq(rps, caps.rp1_freq)); +} + +void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) +{ + if (!rps_uses_slpc(rps)) + return rps_frequency_dump(rps, p); + else + return slpc_frequency_dump(rps, p); +} + static int set_max_freq(struct intel_rps *rps, u32 val) { struct drm_i915_private *i915 = rps_to_i915(rps);
Read the values stored in the SLPC structures. Remove the fields that are no longer valid (like RPS interrupts) as well. v2: Move all functionality changes to this patch (Jani) Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> --- drivers/gpu/drm/i915/gt/intel_rps.c | 46 ++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-)