| Message ID | 20221014230239.1023689-6-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Explicit MCR handling and MTL steering | expand |
On 14.10.2022 16:02, Matt Roper wrote: > There are cases where we wish to read from any non-terminated MCR > register instance (or the primary instance in the case of GAM ranges), > clear/set some bits, and then write the value back out to the register > in a multicast manner. Adding a "multicast RMW" will avoid the need to > open-code this. > > v2: > - Return a u32 to align with the recent change to intel_uncore_rmw. > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 28 ++++++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 3 +++ > 2 files changed, 31 insertions(+) Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Regards, Bala > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > index a2047a68ea7a..4dc360f4e344 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > @@ -302,6 +302,34 @@ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 va > intel_uncore_write_fw(gt->uncore, reg, value); > } > > +/** > + * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations > + * @gt: GT structure > + * @reg: the MCR register to read and write > + * @clear: bits to clear during RMW > + * @set: bits to set during RMW > + * > + * Performs a read-modify-write on an MCR register in a multicast manner. > + * This operation only makes sense on MCR registers where all instances are > + * expected to have the same value. The read will target any non-terminated > + * instance and the write will be applied to all instances. > + * > + * This function assumes the caller is already holding any necessary forcewake > + * domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should > + * be obtained automatically. > + * > + * Returns the old (unmodified) value read. > + */ > +u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg, > + u32 clear, u32 set) > +{ > + u32 val = intel_gt_mcr_read_any(gt, reg); > + > + intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set); > + > + return val; > +} > + > /* > * reg_needs_read_steering - determine whether a register read requires > * explicit steering > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h > index 77a8b11c287d..781b267478db 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h > @@ -24,6 +24,9 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt, > void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, > i915_reg_t reg, u32 value); > > +u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg, > + u32 clear, u32 set); > + > void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, > i915_reg_t reg, > u8 *group, u8 *instance); > -- > 2.37.3 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index a2047a68ea7a..4dc360f4e344 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -302,6 +302,34 @@ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 va intel_uncore_write_fw(gt->uncore, reg, value); } +/** + * intel_gt_mcr_multicast_rmw - Performs a multicast RMW operations + * @gt: GT structure + * @reg: the MCR register to read and write + * @clear: bits to clear during RMW + * @set: bits to set during RMW + * + * Performs a read-modify-write on an MCR register in a multicast manner. + * This operation only makes sense on MCR registers where all instances are + * expected to have the same value. The read will target any non-terminated + * instance and the write will be applied to all instances. + * + * This function assumes the caller is already holding any necessary forcewake + * domains; use intel_gt_mcr_multicast_rmw() in cases where forcewake should + * be obtained automatically. + * + * Returns the old (unmodified) value read. + */ +u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg, + u32 clear, u32 set) +{ + u32 val = intel_gt_mcr_read_any(gt, reg); + + intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set); + + return val; +} + /* * reg_needs_read_steering - determine whether a register read requires * explicit steering diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h index 77a8b11c287d..781b267478db 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h @@ -24,6 +24,9 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt, void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value); +u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg, + u32 clear, u32 set); + void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, i915_reg_t reg, u8 *group, u8 *instance);
There are cases where we wish to read from any non-terminated MCR register instance (or the primary instance in the case of GAM ranges), clear/set some bits, and then write the value back out to the register in a multicast manner. Adding a "multicast RMW" will avoid the need to open-code this. v2: - Return a u32 to align with the recent change to intel_uncore_rmw. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 28 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 3 +++ 2 files changed, 31 insertions(+)