diff mbox series

drm/bridge: tc358767: Set default CLRSIPO count

Message ID 20221016003556.406441-1-marex@denx.de (mailing list archive)
State New, archived
Headers show
Series drm/bridge: tc358767: Set default CLRSIPO count | expand

Commit Message

Marek Vasut Oct. 16, 2022, 12:35 a.m. UTC
The current CLRSIPO count is still marginal and does not work with high
DSI clock rates in burst mode. Increase it further to allow the DSI link
to work at up to 1Gbps lane speed. This returns the counts to defaults
as provided by datasheet.

Fixes: ea6490b02240b ("drm/bridge: tc358767: increase CLRSIPO count")
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
---
 drivers/gpu/drm/bridge/tc358767.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Maxime Ripard Oct. 17, 2022, 6:49 a.m. UTC | #1
On Sun, Oct 16, 2022 at 02:35:56AM +0200, Marek Vasut wrote:
> The current CLRSIPO count is still marginal and does not work with high
> DSI clock rates in burst mode. Increase it further to allow the DSI link
> to work at up to 1Gbps lane speed. This returns the counts to defaults
> as provided by datasheet.
> 
> Fixes: ea6490b02240b ("drm/bridge: tc358767: increase CLRSIPO count")
> Signed-off-by: Marek Vasut <marex@denx.de>

Acked-by: Maxime Ripard <maxime@cerno.tech>

Maxime
diff mbox series

Patch

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 98cfb50a83bec..67f294f96e823 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1267,10 +1267,10 @@  static int tc_dsi_rx_enable(struct tc_data *tc)
 	u32 value;
 	int ret;
 
-	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
-	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
-	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
-	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
+	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
+	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
+	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
+	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
 	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
 	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);